Datasheet

Control Signals
Modem Control Signals
Divisor
Bus
Interface
Control
and
Status Block
Status Signals
Control Signals
Status Signals
Baud Rate
Generator
UART_CLK
Receiver Block
Logic
Receiver FIFO
64-Byte
Vote
Logic
Transmitter Block
Logic
Transmitter FIFO
64-Byte
RX
RX
TX
TX
TL16C752B-EP
SGLS153B –FEBRUARY 2003–REVISED DECEMBER 2007 www.ti.com
TERMINAL FUNCTIONS (continued)
TERMINAL
I/O DESCRIPTION
NAME NO.
Transmit data. These outputs are associated with individual serial transmit channel data from the
TXA, 7,
O TL16C752B. During the local loopback mode, the TX input pin is disabled and TX data is internally
TXB 8
connected to the UART RX input.
TXRDYA, 43, Transmit ready (active low). TXRDY A and B go low when there are at least a trigger level numbers of
O
TXRDYB 6 spaces available. They go high when the TX buffer is full.
V
CC
42 I Power supply inputs
Crystal or external clock input. XTAL1 functions as a crystal input or as an external clock input. A
XTAL1 13 I crystal can be connected between XTAL1 and XTAL2 to form an internal oscillator circuit (see Figure
10). Alternatively, an external clock can be connected to XTAL1 to provide custom data rates.
Output of the crystal oscillator or buffered clock. See also XTAL1. XTAL2 is used as a crystal oscillator
XTAL2 14 O
output or buffered a clock output.
FUNCTIONAL BLOCK DIAGRAM
A. The vote logic determines whether the RX data is a logic 1 or 0. It takes three samples of the RX line and uses a
majority vote to determine the logic level received. The vote logic operates on all bits received.
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