Datasheet

TL16C752B-EP

SGLS153B –FEBRUARY 2003–REVISED DECEMBER 2007

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FIFO Ready Register

The FIFO ready register provides real-time status of the transmit and receive FIFOs of both channels. Table 20

shows the FIFO ready register bit settings. The trigger level mentioned below refers to the setting in either FCR

(when TLR value is zero), or TLR (when it has a nonzero value).

Table 20. FIFO Ready Register

BIT NO. BIT SETTINGS

0 0 = There are less than a TX trigger level number of spaces available in the TX FIFO of channel A.

1 = There are at least a TX trigger level number of spaces available in the TX FIFO of channel A.

1 0 = There are less than a TX trigger level number of spaces available in the TX FIFO of channel B.

1 = There are at least a TX trigger level number of spaces available in the TX FIFO of channel B.

3:2 Unused, always 0

4 0 = There are less than a RX trigger level number of characters in the RX FIFO of channel A.

1 = The RX FIFO of channel A has more than a RX trigger level number of characters available for reading

or a timeout condition has occurred.

5 0 = There are less than a RX trigger level number of characters in the RX FIFO of channel B.

1 = The RX FIFO of channel B has more than a RX trigger level number of characters available for reading

or a timeout condition has occurred.

7:6 Unused, always 0

The FIFORdy register is a read-only register that can be accessed when any of the two UARTs are selected

CSA-B = 0, MCR[2] (FIFO Rdy Enable) is a logic 1 and loopback is disabled. The address is 111.

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