Datasheet
TL16C752B-EP
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SGLS153B –FEBRUARY 2003–REVISED DECEMBER 2007
Transmission Control Register (TCR)
The transmission control register is an 8-bit register that is used to store the receive FIFO threshold levels to
start/stop transmission during hardware/software flow control. Table 18 shows the transmission control register
bit settings.
Table 18. Transmission Control Register (TCR) Bit Settings
BIT NO. BIT SETTINGS
3:0 RCV FIFO trigger level to halt transmission (0–60)
7:4 RCV FIFO trigger level to resume transmission (0–60)
TCR trigger levels are available from 0–60 bytes with a granularity of four.
NOTE
TCR can only be written to when EFR[4] = 1 and MCR[6] = 1. The programmer must
program the TCR such that TCR[3:0] > TCR[7:4]. There is no built-in hardware check to
make sure this condition is met. Also, the TCR must be programmed with this condition
before Auto-RTS or software flow control is enabled to avoid spurious operation of the
device.
Trigger Level Register (TLR)
The trigger level register is an 8-bit register that is pulsed to store the transmit and received FIFO trigger levels
used for DMA and interrupt generation. Trigger levels from 4–60 can be programmed with a granularity of 4.
Table 19 shows the trigger level register bit settings.
Table 19. Trigger Level Register (TLR) Bit Settings
BIT NO. BIT SETTINGS
3:0 Transmit FIFO trigger levels (4–60), number of spaces available
7:4 RCV FIFO trigger levels (4–60), number of characters available
NOTE
TLR can only be written to when EFR[4] = 1 and MCR[6] = 1. If TLR[3:0] or TLR[7:4] are
0, the selectable trigger levels via the FIFO control register (FCR) are used for the
transmit and receive FIFO trigger levels. Trigger levels from 4–60 bytes are available with
a granularity of four. The TLR should be programmed for N/4, where N is the desired
trigger level.
When the trigger level setting in TLR is zero, the TL16C752B uses the trigger level setting defined in FCR. If TLR
has a nonzero trigger level value, the trigger level defined in FCR is discarded. This applies to both the transmit
FIFO and receive FIFO trigger level setting.
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