Datasheet

TL16C752B-EP
SGLS153B –FEBRUARY 2003–REVISED DECEMBER 2007 www.ti.com
When the LSR is read, LSR[4:2] reflect the error bits [BI, FE, PE] of the character at the top of the RX FIFO (next
character to be read). The LSR[4:2] registers do not physically exist, as the data read from the RX FIFO is output
directly onto the output data-bus, DI[4:2], when the LSR is read. Therefore, errors in a character are identified by
reading the LSR and then reading the RHR.
LSR[7] is set when there is an error anywhere in the RX FIFO and is cleared only when there are no more errors
remaining in the FIFO.
NOTE
Reading the LSR does not cause an increment of the RX FIFO read pointer. The RX FIFO
read pointer is incremented by reading the RHR.
NOTE
TI has found that the three error bits (parity, framing, break) may not be updated correctly
in the first read of the LSR when the input clock (Xtal1) is running faster than 36 MHz.
However, the second read should be correct. It is strongly recommended that when using
this device with a clock faster than 36 MHz, that the LSR be read twice and only the
second read be used for decision making. All other bits in the LSR should be correct on all
reads.
Modem Control Register (MCR)
The MCR controls the interface with the modem, data set, or peripheral device that is emulating the modem.
Table 12 shows the modem control register bit settings.
Table 12. Modem Control Register (MCR) Bit Settings
BIT NO. BIT SETTINGS
0 0 = Force DTR output to inactive (high)
1 = Force DTR output to active (low)
In loopback controls MSR[5].
1 0 = Force RTS output to inactive (high)
1 = Force RTS output to active (low)
In loopback controls MSR[4]
If Auto-RTS is enabled the RTS output is controlled by hardware flow control
2 0 Disables the FIFO Rdy register
1 Enable the FIFO Rdy register
In loopback controls MSR[6].
3 0 = Forces the INT(A - B) outputs to 3-state and OP output to high state
1 = Forces the INT(A - B) outputs to the active state and OP output to low state
In loopback controls MSR[7].
4 0 = Normal operating mode
1 = Enable local loopback mode (internal)
In this mode the MCR[3:0] signals are looped back into MSR[3:0] and the TX output is looped back to the RX input
internally.
5 0 = Disable Xon any function
1 = Enable Xon any function
6 0 = No action
1 = Enable access to the TCR and TLR registers
7 0 = Divide by one clock input
1 = Divide by four clock input
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