Datasheet

TL16C752B-EP
www.ti.com SGLS153B –FEBRUARY 2003–REVISED DECEMBER 2007
Table 8 lists and describes the TL16C752B internal registers.
Table 8. TL16C752B Internal Registers
(1) (2)
Addr RGTR BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 READ/WR
ITE
000 RHR Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Read
000 THR Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Write
001 IER 0/CTS 0/RTS 0/Xoff 0/X Sleep Modem Rx line THR Rx data Read/Writ
interrupt interrupt sleep mode status status empty available e
enable enable mode interrupt interrupt interrupt interrupt
010 FCR Rx trigger Rx trigger 0/TX 0/TX DMA Resets Tx Resets Rx Enables Write
level level trigger trigger mode FIFO FIFO FIFOs
level level select
010 IIR FCR(0) FCR(0) 0/CTS, 0/Xoff? Interrupt Interrupt Interrupt Interrupt Read
RTS? priority Bit priority Bit priority Bit status
2 1 0
011 LCR DLAB and Break Sets parity Parity type Parity Number of Word Word Read/Writ
EFR control Bit select enable stop Bits length length e
enable
100 MCR 1x or 1x/4 TCR and 0/Xon Any 0/Enable IRQ FIFO Rdy RTS DTR Read/Writ
clock TLR loopback enable OP enable e
enable
101 LSR 0/Error in THR and THR Break Framing Parity error Overrun Data in Read
Rx FIFO TSR empty interrupt error error receiver
empty
110 MSR CD RI DSR CTS ΔCD ΔRI ΔDSR ΔCTS Read
111 SPR Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Read/Writ
e
000 DLL Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Read/Writ
e
001 DLH Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Read/Writ
e
010 EFR Auto-CTS Auto-RTS Special Enable S/W flow S/W flow S/W flow S/W flow Read/Writ
character enhanced control Bit control Bit control Bit control Bit e
detect functions 3 2 1 0
100 Xon1 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Read/Writ
e
101 Xon2 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Read/Writ
e
110 Xoff1 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Read/Writ
e
111 Xoff2 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Read/Writ
e
110 TCR Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Read/Writ
e
111 TLR Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Read/Writ
e
111 FIFO Rdy 0 0 RX FIFO RX FIFO 0 0 TX FIFO TX FIFO Read
B status A status B status A status
(1) The shaded bits can be modified only if register bit EFR[4] is enabled, i.e., if enhanced functions are enabled.
(2) See the notes under Table 7 for more register access information.
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