Datasheet

Start
Bit
Parity
Bit
Stop
Bit
Next
Data
Start
Bit
Data Bits (5−8)
t
d17
t
d18
TX (A−B)
TXRDY
(A−B)
IOW
D0 D1 D2 D3 D4 D5 D6 D7
Active
Transmitter
Not Ready
Byte 1
Active
Transmitter Ready
D0−D7
Start
Bit
5 Data Bits
6 Data Bits
7 Data Bits
Parity
Bit
Stop
Bit
Next
Data
Start
Bit
Data Bits (5−8)
t
d12
t
d14
16 Baud Rate Clock
TX (A−B)
INT (A−B)
IOW
D0 D1 D2 D3 D4 D5 D6 D7
Active
Tx Ready
Active
t
d13
Active
TL16C752B-EP
SGLS153B –FEBRUARY 2003–REVISED DECEMBER 2007 www.ti.com
TYPICAL CHARACTERISTICS (continued)
Figure 18. Transmit Timing
Figure 19. Transmit Ready Timing in Non-FIFO Mode
22 Submit Documentation Feedback Copyright © 2003–2007, Texas Instruments Incorporated
Product Folder Links: TL16C752B-EP