Datasheet

Start
Bit
Parity
Bit
Stop
Bit
First Byte
That Reaches
the Trigger
Level
Data Bits (5−8)
t
d15
t
d16
RX (A−B)
RXRDY
(A−B)
RXRDY
IOR
D0 D1 D2 D3 D4 D5 D6 D7
Active
Data
Ready
Active
Start
Bit
Parity
Bit
Stop
Bit
Next
Data
Start
Bit
Data Bits (5−8)
t
d15
t
d16
RX (A−B)
RXRDY
(A−B)
RXRDY
IOR
D0 D1 D2 D3 D4 D5 D6 D7
Active
Data
Ready
Active
TL16C752B-EP
www.ti.com SGLS153B –FEBRUARY 2003–REVISED DECEMBER 2007
TYPICAL CHARACTERISTICS (continued)
Figure 16. Receive Ready Timing in Non-FIFO Mode
Figure 17. Receive Timing in FIFO Mode
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Product Folder Links: TL16C752B-EP