Datasheet

Prescaler Logic
(Divide By 1)
Prescaler Logic
(Divide By 4)
Internal
Oscillator
Logic
Baud Rate
Generator
Logic
XTAL1
XTAL2
MCR[7] = 0
MCR[7] = 1
Input Clock
Reference
Clock
divisor = (XTAL1 crystal input frequency/prescaler) / (desired baud rate × 16)
where:
prescaler +
ȥ
ȡ
Ȣ
1, when MCR[7] is set to 0 after reset (divide-by-1 clock selected)
4, when MCR[7] is set to 1 after reset (divide-by-4 clock selected)
TL16C752B-EP
SGLS153B –FEBRUARY 2003–REVISED DECEMBER 2007 www.ti.com
Programmable Baud Rate Generator
The TL16C752B UART contains a programmable baud generator that takes any clock input and divides it by a
divisor in the range between 1 and (2
16
–1). An additional divide-by-4 prescaler is also available and can be
selected by MCR[7], as shown in Figure 9 . The output frequency of the baud rate generator is 16× the baud
rate. The formula for the divisor is:
(1)
NOTE
The default value of prescaler after reset is divide-by-1.
Figure 9 shows the internal prescaler and baud rate generator circuitry.
Figure 9. Prescaler and Baud Rate Generator Block Diagram
DLL and DLH must be written to in order to program the baud rate. DLL and DLH are the least significant and
most significant byte of the baud rate divisor. If DLL and DLH value are both zero, the UART is effectively
disabled, as no baud clock is generated.
NOTE
The programmable baud rate generator is provided to select both the transmit and receive
clock rates.
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