Datasheet

1111
IER
IIR
THR RHR
IOW/IOR
INTProcessor
TL16C752B-EP
www.ti.com SGLS153B –FEBRUARY 2003–REVISED DECEMBER 2007
Interrupts
The TL16C752B has interrupt generation and prioritization (6 prioritized levels of interrupts) capability. The
interrupt enable register (IER) enables each of the 6 types of interrupts and the INT signal in response to an
interrupt generation. The IER can also disable the interrupt system by clearing bits 0–3, 5–7. When an interrupt
is generated, the IIR indicates that an interrupt is pending and provides the type of interrupt through IIR[5–0].
Table 4 summarizes the interrupt control functions.
Table 4. Interrupt Control Functions
PRIORITY INTERRUPT
IIR[5–0] INTERRUPT SOURCE INTERRUPT RESET METHOD
LEVEL TYPE
000001 None None None None
000110 1 Receiver line OE, FE, PE, or BI errors occur in characters in FE, PE, BI: All erroneous characters are read
status the RX FIFO from the RX FIFO.
OE: Read LSR
001100 2 RX timeout Stale data in RX FIFO Read RHR
000100 2 RHR DRDY (data ready) Read RHR
interrupt (FIFO disable)
RX FIFO above trigger level (FIFO enable)
000010 3 THR interrupt TFE (THR empty)(FIFO disable)TX FIFO passes Read IIR OR a write to the THR
above trigger level (FIFO enable)
000000 4 Modem MSR[3:0] = 0 Read MSR
status
010000 5 Xoff interrupt Receive Xoff character(s)/special character Receive Xon character(s)/Read of IIR
100000 6 CTS, RTS RTS pin or CTS pin change state from active Read IIR
(low) to inactive (high)
It is important to note that for the framing error, parity error, and break conditions, LSR[7] generates the interrupt.
LSR[7] is set when there is an error anywhere in the RX FIFO and is cleared only when there are no more errors
remaining in the FIFO. LSR[4–2] always represent the error status for the received character at the top of the RX
FIFO. Reading the RX FIFO updates LSR[4–2] to the appropriate status for the new character at the top of the
FIFO. If the RX FIFO is empty, then LSR[4–2] are all zeros.
For the Xoff interrupt, if an Xoff flow character detection caused the interrupt, the interrupt is cleared by an Xon
flow character detection. If a special character detection caused the interrupt, the interrupt is cleared by a read of
the LSR
Interrupt Mode Operation
In interrupt mode (if any bit of IER[3:0] is 1) the processor is informed of the status of the receiver and transmitter
by an interrupt signal, INT. Therefore, it is not necessary to continuously poll the line stats register (LSR) to see if
any interrupt needs to be serviced. Figure 5 shows interrupt mode operation.
Figure 5. Interrupt Mode Operation
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