Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsLinear ICsTL16C752BTPTREP

14 15

RESET

DTRB

DTRA

RTSA

OPA

RXRDYA

INTA

INTB

RXB

RXA

TXRDYB

TXA

TXB

OPB

CSA

CSB

17 18 19 20

RIA

CDA

DSRA

CTSA

47 46 45 44 4348 42

RTSB

CTSB

IOW

GND

RXRDYB

IOR

DSRB

RIB

40 39 3841

21 22 23 24

TXRDYA

XTAL2

XTAL1

CDB

PACKAGE

(TOP VIEW)

NC − No internal connection

TL16C752B-EP

www.ti.com

SGLS153B –FEBRUARY 2003–REVISED DECEMBER 2007

3.3 V DUAL UART WITH 64-BYTE FIFO

Check for Samples: TL16C752B-EP

FEATURES

• Controlled Baseline • Fast Access Time 2 Clock Cycle IOR/IOW

Pulse Width

– One Assembly Site

• Programmable Sleep Mode

– Test Site

• Programmable Serial Interface Characteristics

– One Fabrication Site

– 5-Bit, 6-Bit, 7-Bit, or 8-Bit Characters

• Extended Temperature Performance of

–55°C to 110°C and –40°C to 105°C – Even, Odd, or No Parity Bit Generation and

Detection

• Enhanced Diminishing Manufacturing Sources

(DMS) Support – 1, 1.5, or 2 Stop Bit Generation

• Enhanced Product Change Notification • False Start Bit Detection

• Qualification Pedigree

(1)

• Complete Status Reporting Capabilities in

Both Normal and Sleep Mode

• Pin Compatible With ST16C2550 With

Additional Enhancements • Line Break Generation and Detection

• Up to 1.5-Mbps Baud Rate When Using Crystal • Internal Test and Loopback Capabilities

(24-MHz Input Clock)

• Fully Prioritized Interrupt System Controls

• Up to 3-Mbps Baud Rate When Using

• Modem Control Functions (CTS, RTS, DSR,

Oscillator or Clock Source (48-MHz Input

DTR, RI, and CD)

Clock)

• 64-Byte Transmit FIFO

• 64-Byte Receive FIFO With Error Flags

• Programmable and Selectable Transmit and

Receive FIFO Trigger Levels for DMA and

Interrupt Generation

• Programmable Receive FIFO Trigger Levels for

Software/Hardware Flow Control

• Software/Hardware Flow Control

– Programmable Xon/Xoff Characters

– Programmable Auto-RTS and Auto-CTS

• Optional Data Flow Resume by Xon Any

Character

• DMA Signaling Capability for Both Received

and Transmitted Data

• Supports 3.3-V Operation

• Software Selectable Baud Rate Generator

• Prescaler Provides Additional Divide By Four

Function

(1) Component qualification in accordance with JEDEC and

industry standards to ensure reliable operation over an

extended temperature range. This includes, but is not limited

to, Highly Accelerated Stress Test (HAST) or biased 85/85,

temperature cycle, autoclave or unbiased HAST,

electromigration, bond intermetallic life, and mold compound

life. Such qualification testing should not be viewed as

justifying use of this component beyond specified

performance and environmental limits.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (40 pages)

PAGE 1
TL16C752B-EP www.ti.com SGLS153B – FEBRUARY 2003 – REVISED DECEMBER 2007 3.3 V DUAL UART WITH 64-BYTE FIFO Check for Samples: TL16C752B-EP FEATURES 1 • • • • • • • • • • • • • • • • (1) Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range.
PAGE 2
TL16C752B-EP SGLS153B – FEBRUARY 2003 – REVISED DECEMBER 2007 www.ti.com DESCRIPTION/ORDERING INFORMATION The TL16C752B is a dual-universal asynchronous receiver/transmitter (UART) with 64-byte FIFOs, automatic hardware/software flow control, and data rates up to 3 Mbps. The TL16C752B offers enhanced features. It has a transmission control register (TCR) that stores receiver FIFO threshold levels to start/stop transmission during hardware and software flow control.
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TL16C752B-EP www.ti.com SGLS153B – FEBRUARY 2003 – REVISED DECEMBER 2007 TERMINAL FUNCTIONS TERMINAL NAME NO. I/O DESCRIPTION A0 28 I Address 0 select bit. Internal registers address selection. A1 27 I Address 1 select bit. Internal registers address selection. A2 26 I Address 2 select bit. Internal registers address selection. CDA, CDB 40, 16 I Carrier detect (active low). These inputs are associated with individual UART channels A and B.
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TL16C752B-EP SGLS153B – FEBRUARY 2003 – REVISED DECEMBER 2007 www.ti.com TERMINAL FUNCTIONS (continued) TERMINAL NAME NO. I/O DESCRIPTION TXA, TXB 7, 8 O Transmit data. These outputs are associated with individual serial transmit channel data from the TL16C752B. During the local loopback mode, the TX input pin is disabled and TX data is internally connected to the UART RX input. TXRDYA, TXRDYB 43, 6 O Transmit ready (active low).
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TL16C752B-EP www.ti.com SGLS153B – FEBRUARY 2003 – REVISED DECEMBER 2007 FUNCTIONAL DESCRIPTION The TL16C752B UART is pin-compatible with the ST16C2550 UART. It provides more enhanced features. All additional features are provided through a special enhanced feature register. The UART performs a serial-to-parallel conversion on data characters received from peripheral devices or modems and parallel-to-parallel conversion on data characters transmitted by the processor.
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TL16C752B-EP SGLS153B – FEBRUARY 2003 – REVISED DECEMBER 2007 Start RX Byte N Stop www.ti.com Start Byte N+1 Stop Start RTS IOR 1 2 N N+1 A. N = receiver FIFO trigger level 2. B. The two blocks in dashed lines cover the case where an additional byte is sent as described in Auto-RTS. Figure 1. RTS Functional Timing Auto-CTS The transmitter circuitry checks CTS before sending the next data byte. When CTS is active, the transmitter sends the next byte.
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TL16C752B-EP www.ti.com SGLS153B – FEBRUARY 2003 – REVISED DECEMBER 2007 UART 1 UART 2 Serial to Parallel RX TX Parallel to Serial RX FIFO TX FIFO Flow Control RTS CTS Flow Control D7−D0 D7−D0 Parallel to Serial TX RX Serial to Parallel TX FIFO RX FIFO Flow Control CTS RTS Flow Control Figure 3. Autoflow Control (Auto-RTS and Auto-CTS) Example Software Flow Control Software flow control is enabled through the enhanced feature register and the modem control register.
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TL16C752B-EP SGLS153B – FEBRUARY 2003 – REVISED DECEMBER 2007 www.ti.com Table 1.
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TL16C752B-EP www.ti.com SGLS153B – FEBRUARY 2003 – REVISED DECEMBER 2007 UART 1 UART 2 Transmit FIFO Receive FIFO Parallel to Serial Data Serial to Parallel Xoff − Xon − Xoff Serial to Parallel Parallel to Serial Xon-1 Word Xon-1 Word Xon-2 Word Xon-2 Word Xoff-1 Word Xoff-1 Word Xoff-1 Word Compare Programmed Xon−Xoff Characters Xoff-2 Word Figure 4. Software Flow Control Example Software Flow Control Example Assumptions: UART1 is transmitting a large text file to UART2.
PAGE 10
TL16C752B-EP SGLS153B – FEBRUARY 2003 – REVISED DECEMBER 2007 www.ti.com Reset Table 2 summarizes the state of registers after reset. Table 2. Register Reset Functions (1) RESET CONTROL REGISTER RESET STATE Interrupt enable register RESET All bits cleared Interrupt identification register RESET Bits 0 is set. All other bits cleared. FIFO control register RESET All bits cleared Line control register RESET Reset to 00011101 (1D hex).
PAGE 11
TL16C752B-EP www.ti.com SGLS153B – FEBRUARY 2003 – REVISED DECEMBER 2007 Interrupts The TL16C752B has interrupt generation and prioritization (6 prioritized levels of interrupts) capability. The interrupt enable register (IER) enables each of the 6 types of interrupts and the INT signal in response to an interrupt generation. The IER can also disable the interrupt system by clearing bits 0–3, 5–7.
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TL16C752B-EP SGLS153B – FEBRUARY 2003 – REVISED DECEMBER 2007 www.ti.com Polled Mode Operation In polled mode (IER[3:0]=0000) the status of the receiver and transmitter can be checked by polling the line status register (LSR). This mode is an alternative to the FIFO interrupt mode of operation where the status of the receiver and transmitter is automatically known by means of interrupts sent to the CPU. Figure 6 shows FIFO polled mode operation. LSR IOW/IOR Processor IER 0 0 THR 0 0 RHR Figure 6.
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TL16C752B-EP www.ti.com SGLS153B – FEBRUARY 2003 – REVISED DECEMBER 2007 Block DMA Transfers (DMA Mode 1) Transmitter: TXRDY is active when there is a trigger level number of spaces available. It becomes inactive when the FIFO is full. Receiver: RXRDY becomes active when the trigger level has been reached or when a timeout interrupt occurs. It goes inactive when the FIFO is empty or an error in the RX FIFO is flagged by LSR(7) Figure 8 shows TXRDY and RXRDY in DMA mode 1.
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TL16C752B-EP SGLS153B – FEBRUARY 2003 – REVISED DECEMBER 2007 www.ti.com Programmable Baud Rate Generator The TL16C752B UART contains a programmable baud generator that takes any clock input and divides it by a divisor in the range between 1 and (216–1). An additional divide-by-4 prescaler is also available and can be selected by MCR[7], as shown in Figure 9 . The output frequency of the baud rate generator is 16× the baud rate.
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TL16C752B-EP www.ti.com SGLS153B – FEBRUARY 2003 – REVISED DECEMBER 2007 Table 5 and Table 6 show the baud rate and divisor correlation for crystal with frequency 1.8432 MHz and 3.072 MHz respectively. Figure 10 shows the crystal clock circuit reference. Table 5. Baud Rates Using a 1.8432-MHz Crystal DESIRED BAUD RATE DIVISOR USEDTO GENERATE 16× CLOCK 50 2304 PERCENT ERROR DIFFERENCE BETWEEN DESIRED AND ACTUAL 75 1536 110 1047 0.026 134.5 857 0.
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TL16C752B-EP SGLS153B – FEBRUARY 2003 – REVISED DECEMBER 2007 VCC VCC Driver External Clock www.ti.com XTAL1 XTAL1 C1 Crystal RP Optional Clock Output Optional Driver XTAL2 RX2 Oscillator Clock to Baud Generator Logic Oscillator Clock to Baud Generator Logic XTAL2 C2 A. For crystal with fundamental frequency from 1 MHz to 24 MHz B.
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TL16C752B-EP www.ti.com SGLS153B – FEBRUARY 2003 – REVISED DECEMBER 2007 RECOMMENDED OPERATING CONDITIONS Low voltage (3.3 V nominal) (unless otherwise noted) VCC Supply voltage VI Input voltage VIH High-level input voltage (1) VIL Low-level input voltage (1) VO Output voltage (2) NOM 2.7 3.3 UNIT 3.6 V VCC V 0.7 VCC VCC V 0.3 VCC V VCC V 0 VCC – 0.8 IOH = –4 mA (4) VCC – 0.8 High-level output current MAX 0 (3) IOH = –8 mA VOH MIN V IOL = –8 mA (3) 0.
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TL16C752B-EP SGLS153B – FEBRUARY 2003 – REVISED DECEMBER 2007 www.ti.com TIMING REQUIREMENTS TA = –55°C to 110°C (L device) , –40°C to 105°C (T device) VCC = 3.
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TL16C752B-EP www.ti.com A0−A2 ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ Valid th4 Active td1 th1 tw1 IOR ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ td2 Active td3 D0−D7 SGLS153B – FEBRUARY 2003 – REVISED DECEMBER 2007 TYPICAL CHARACTERISTICS tsu1 CS (A−B) ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ td4 Data Figure 11.
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TL16C752B-EP SGLS153B – FEBRUARY 2003 – REVISED DECEMBER 2007 www.ti.com TYPICAL CHARACTERISTICS (continued) IOW Active td7 RTS (A−B) DTR (A−B) Change of State Change of State CD (A−B) CTS (A−B) DSR (A−B) Change of State td8 td8 INT (A−B) Active Active Active td9 Active IOR Active Active td8 RI (A−B) Change of State Figure 14.
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TL16C752B-EP www.ti.com SGLS153B – FEBRUARY 2003 – REVISED DECEMBER 2007 TYPICAL CHARACTERISTICS (continued) Stop Bit Start Bit Data Bits (5−8) D0 RX (A−B) D1 D2 D3 D4 D5 D6 D7 Parity Bit Next Data Start Bit td15 Active Data Ready RXRDY (A−B) RXRDY td16 Active IOR Figure 16.
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TL16C752B-EP SGLS153B – FEBRUARY 2003 – REVISED DECEMBER 2007 www.ti.com TYPICAL CHARACTERISTICS (continued) Start Bit Stop Bit Data Bits (5−8) D0 TX (A−B) D1 D2 D3 D4 D5 D6 D7 Parity Bit 5 Data Bits 6 Data Bits Next Data Start Bit 7 Data Bits td12 Active Tx Ready INT (A−B) td13 td14 Active Active IOW 16 Baud Rate Clock Figure 18.
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TL16C752B-EP www.ti.com SGLS153B – FEBRUARY 2003 – REVISED DECEMBER 2007 TYPICAL CHARACTERISTICS (continued) Start Bit Stop Bit Data Bits (5−8) D0 TX (A−B) D1 D2 D3 D4 D5 D6 D7 Parity Bit 5 Data Bits 6 Data Bits 7 Data Bits IOW D0−D7 Active Byte 32 td18 td17 TXRDY (A−B) Trigger Lead Figure 20. Transmit Ready Timing in FIFO Mode Timing Error Condition Texas Instruments has discovered a timing anomaly in the TL16C752B.
PAGE 24
TL16C752B-EP SGLS153B – FEBRUARY 2003 – REVISED DECEMBER 2007 www.ti.com PRINCIPLES OF OPERATION Register Map (1) Each register is selected using address lines A[0], A[1], A[2], and in some cases, bits from other registers. The programming combinations for register selection are shown in Table 7. All registers shown in bold are accessed by a combination of address pins and register bits. Table 7.
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TL16C752B-EP www.ti.com SGLS153B – FEBRUARY 2003 – REVISED DECEMBER 2007 Table 8 lists and describes the TL16C752B internal registers. Table 8.
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TL16C752B-EP SGLS153B – FEBRUARY 2003 – REVISED DECEMBER 2007 www.ti.com Receiver Holding Register (RHR) and The Receiver Shift Register (RSR) The receiver section consists of the receiver holding register (RHR) and the receiver shift register (RSR). The RHR is actually a 64-byte FIFO. The RSR receives serial data from the RX terminal. The data is converted to parallel data and moved to the RHR. The receiver section is controlled by the line control register.
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TL16C752B-EP www.ti.com SGLS153B – FEBRUARY 2003 – REVISED DECEMBER 2007 Line Control Register (LCR) The line control register controls the data communication format. The word length, number of stop bits, and parity type are selected by writing the appropriate bits to the LCR. Table 10 shows the line control register bit settings. Table 10. TL16C752B Internal Registers BIT NO. 1:0 BIT SETTINGS Specifies the word length to be transmitted or received.
PAGE 28
TL16C752B-EP SGLS153B – FEBRUARY 2003 – REVISED DECEMBER 2007 www.ti.com When the LSR is read, LSR[4:2] reflect the error bits [BI, FE, PE] of the character at the top of the RX FIFO (next character to be read). The LSR[4:2] registers do not physically exist, as the data read from the RX FIFO is output directly onto the output data-bus, DI[4:2], when the LSR is read. Therefore, errors in a character are identified by reading the LSR and then reading the RHR.
PAGE 29
TL16C752B-EP www.ti.com SGLS153B – FEBRUARY 2003 – REVISED DECEMBER 2007 Modem Status Register (MSR) The modem status register is an 8-bit register that provides information about the current state of the control lines from the modem, data set, or peripheral device to the processor. It also indicates when a control input from the modem changes state. Table 13 shows the modem status register bit settings per channel. Table 13. Modem Status Register (MSR) Bit Settings BIT NO.
PAGE 30
TL16C752B-EP SGLS153B – FEBRUARY 2003 – REVISED DECEMBER 2007 www.ti.com Interrupt IdentificationRegister (IIR) The interrupt identification register is a read-only 8-bit register, which provides the source of the interrupt in a prioritized manner. Table 15 shows the IIR bit settings. Table 15. Interrupt Identification Register (IIR) Bit Settings BIT NO. BIT SETTINGS 0 0 = A interrupt is pending 1 = No interrupt is pending 3:1 3-Bit encoded interrupt. See Table 14.
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TL16C752B-EP www.ti.com SGLS153B – FEBRUARY 2003 – REVISED DECEMBER 2007 Transmission Control Register (TCR) The transmission control register is an 8-bit register that is used to store the receive FIFO threshold levels to start/stop transmission during hardware/software flow control. Table 18 shows the transmission control register bit settings. Table 18. Transmission Control Register (TCR) Bit Settings BIT NO.
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TL16C752B-EP SGLS153B – FEBRUARY 2003 – REVISED DECEMBER 2007 www.ti.com FIFO Ready Register The FIFO ready register provides real-time status of the transmit and receive FIFOs of both channels. Table 20 shows the FIFO ready register bit settings. The trigger level mentioned below refers to the setting in either FCR (when TLR value is zero), or TLR (when it has a nonzero value). Table 20. FIFO Ready Register BIT NO.
PAGE 33
TL16C752B-EP www.ti.com SGLS153B – FEBRUARY 2003 – REVISED DECEMBER 2007 TL16C752B Programmer's Guide The base set of registers that is used during high speed data transfer have a straightforward access method. The extended function registers require special access bits to be decoded along with the address lines. The following guide helps with programming these registers. Note that the descriptions below are for individual register access.
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TL16C752B-EP SGLS153B – FEBRUARY 2003 – REVISED DECEMBER 2007 Set prescaler value to divide-by-four 34 www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TL16C752BLPTREP LQFP PT 48 1000 330.0 16.4 9.6 9.6 1.9 12.0 16.0 Q1 TL16C752BTPTREP LQFP PT 48 1000 330.0 16.4 9.6 9.6 1.9 12.0 16.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TL16C752BLPTREP LQFP PT 48 1000 367.0 367.0 38.0 TL16C752BTPTREP LQFP PT 48 1000 367.0 367.0 38.
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MECHANICAL DATA MTQF003A – OCTOBER 1994 – REVISED DECEMBER 1996 PT (S-PQFP-G48) PLASTIC QUAD FLATPACK 0,27 0,17 0,50 36 0,08 M 25 37 24 48 13 0,13 NOM 1 12 5,50 TYP 7,20 SQ 6,80 9,20 SQ 8,80 Gage Plane 0,25 0,05 MIN 1,45 1,35 Seating Plane 1,60 MAX 0°– 7° 0,75 0,45 0,10 4040052 / C 11/96 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.