Datasheet

TL16C752B

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SLLS405C –DECEMBER 1999–REVISED JUNE 2010

Software Flow Control Example

Assumptions: UART1 is transmitting a large text file to UART2. Both UARTs are using software flow control with

single character Xoff (0F) and Xon (0D) tokens. Both have Xoff threshold (TCR [3:0]=F) set to 60 and Xon

threshold (TCR[7:4]=8) set to 32. Both have the interrupt receive threshold (TLR[7:4]=D) set to 52.

UART1 begins transmission and sends 52 characters, at which point UART2 will generate an interrupt to its

processor to service the RCV FIFO, but assume the interrupt latency is fairly long. UART1 will continue sending

characters until a total of 60 characters have been sent. At this time UART2 will transmit a 0F to UART1,

informing UART1 to halt transmission. UART1 will likely send the 61st character while UART2 is sending the Xoff

character. Now UART2 is serviced and the processor reads enough data out of the RCV FIFO that the level

drops to 32. UART2 will now send a 0D to UART1, informing UART1 to resume transmission.

Reset

Table 2 summarizes the state of registers after reset.

Table 2. Register Reset Functions

(1)

Interrupt enable register RESET All bits cleared

Interrupt identification register RESET Bit 0 is set. All other bits cleared.

FIFO control register RESET All bits cleared

Line control register RESET Reset to 00011101 (1D hex).

Modem control register RESET All bits cleared

Line status register RESET Bits 5 and 6 set. All other bits cleared.

Modem status register RESET Bits 0-3 cleared. Bits 4-7 input signals.

Enhanced feature register RESET All bits cleared

Receiver holding register RESET Pointer logic cleared

Transmitter holding register RESET Pointer logic cleared

Transmission control register RESET All bits cleared

Trigger level register RESET All bits cleared

(1) Registers DLL, DLH, SPR, Xon1, Xon2, Xoff1, Xoff2 are not reset by the top-level reset signal RESET,

i.e., they hold their initialization values during reset.

Table 3 summarizes the state of registers after reset.

Table 3. Signal Reset Functions

SIGNAL RESET CONTROL RESET STATE

TX RESET High

RTS RESET High

DTR RESET High

RXRDY RESET High

TXRDY RESET Low

Interrupts

The TL16C752B has interrupt generation and prioritization (6 prioritized levels of interrupts) capability. The

interrupt enable register (IER) enables each of the 6 types of interrupts and the INT signal in response to an

interrupt generation. The IER can also disable the interrupt system by clearing bits 0–3, 5–7. When an interrupt

is generated, the IIR indicates that an interrupt is pending and provides the type of interrupt through IIR[5–0].

Table 4 summarizes the interrupt control functions.

Product Folder Link(s): TL16C752B