Datasheet

TL16C752B
SLLS405C –DECEMBER 1999–REVISED JUNE 2010 www.ti.com
FIFO Ready Register
The FIFO ready register provides real-time status of the transmit and receive FIFOs of both channels. Table 20
shows the FIFO ready register bit settings. The trigger level mentioned below refers to the setting in either FCR
(when TLR value is zero), or TLR (when it has a nonzero value).
Table 20. FIFO Ready Register
BIT NO. BIT SETTINGS
(1)
0 0 = There are less than a TX trigger level number of spaces available in the TX FIFO of channel A.
1 = There are at least a TX trigger level number of spaces available in the TX FIFO of channel A.
1 0 = There are less than a TX trigger level number of spaces available in the TX FIFO of channel B.
1 = There are at least a TX trigger level number of spaces available in the TX FIFO of channel B.
3:2 Unused, always 0
4 0 = There are less than a RX trigger level number of characters in the RX FIFO of channel A.
1 = The RX FIFO of channel A has more than a RX trigger level number of characters available for reading or a timeout
condition has occurred.
5 0 = There are less than a RX trigger level number of characters in the RX FIFO of channel B.
1 = The RX FIFO of channel B has more than a RX trigger level number of characters available for reading or a timeout
condition has occurred.
7:6 Unused, always 0
(1) IER[7:4] can only be modified if EFR[4] is set, i.e., EFR[4] is a write enable. Re-enabling IER[1] will not cause a new interrupt if the THR
is below the threshold.
The FIFORdy register is a read-only register that can be accessed when any of the two UARTs are selected
CSA-B = 0, MCR[2] (FIFO Rdy Enable) is a logic 1 and loopback is disabled. The address is 111.
TL16C752 PROGRAMMER'S GUIDE
The base set of registers that is used during high speed data transfer have a straightforward access method. The
extended function registers require special access bits to be decoded along with the address lines. The following
guide will help with programming these registers. Note that the descriptions below are for individual register
access. Some streamlining through interleaving can be obtained when programming all the registers.
Set baud rate to VALUE1, VALUE2 Read LCR (03), save in temp
Set LCR (03) to 80
Set DLL (00) to VALUE1
Set DLM (01) to VALUE2
Set LCR (03) to temp
Set Xoff1, Xon1 to VALUE1, VALUE2 Read LCR (03), save in temp
Set LCR (03) to BF
Set Xoff1 (06) to VALUE1
Set Xon1 (04) to VALUE2
Set LCR (03) to temp
Set Xoff2, Xon2 to VALUE1, VALUE2 Read LCR (03), save in temp
Set LCR (03) to BF
Set Xoff2 (07) to VALUE1
Set Xon2 (05) to VALUE2
Set LCR (03) to temp
Set software flow control mode to VALUE Read LCR (03), save in temp
Set LCR (03) to BF
Set EFR (02) to VALUE
Set LCR (03) to temp
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