Datasheet

TL16C752B

SLLS405C –DECEMBER 1999–REVISED JUNE 2010

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The interrupt priority list is illustrated in Table 16.

Table 16. Interrupt Priority List

PRIORITY

BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 INTERRUPT SOURCE

LEVEL

1 0 0 0 1 1 0 Receiver line status error

2 0 0 1 1 0 0 Receiver timeout interrupt

2 0 0 0 1 0 0 RHR interrupt

3 0 0 0 0 1 0 THR interrupt

4 0 0 0 0 0 0 Modem interrupt

5 0 1 0 0 0 0 Received Xoff signal/special character

6 1 0 0 0 0 0 CTS, RTS change of state from active (low) to inactive (high).

Enhanced Feature Register (EFR)

This 8-bit register enables or disables the enhanced features of the UART. Table 17 shows the enhanced feature

Table 17. Enhanced Feature Register (EFR) Bit Settings

BIT NO. BIT SETTINGS

(1)

3:0 Combinations of software flow control can be selected by programming bit 3-bit 0. See Table 1.

4 Enhanced functions enable bit

0 = Disables enhanced functions and writing to IER bits 4-7, FCR bits 4-5, MCR bits 5-7.

1 = Enables the enhanced function IER bits 4-7, FCR bit 4-5, and MCR bits 5-7 can be modified, i.e., this bit is therefore a

write enable.

5 0 = Normal operation

1 = Special character detect. Received data is compared with Xoff-2 data. If a match occurs the received data is transferred

to FIFO and IIR bit 4 is set to 1 to indicate a special character has been detected.

6 RTS flow control enable bit

0 = Normal operation

1 = RTS flow control is enabled i.e., RTS pin goes high when the receiver FIFO HALT trigger level TCR[3:0] is reached, and

goes low when the receiver FIFO RESTORE transmission trigger level TCR[7:4] is reached.

7 CTS flow control enable bit

0 = Normal operation

1 = CTS flow control is enabled i.e., transmission is halted when a high signal is detected on the CTS pin.

(1) IER[7:4] can only be modified if EFR[4] is set, i.e., EFR[4] is a write enable. Re-enabling IER[1] will not cause a new interrupt if the THR

is below the threshold.

Divsor Latched (DLL, DLH)

These are two 8-bit registers which store the 16-bit divisor for generation of the baud clock in the baud rate

generator. DLH, stores the most significant part of the divisor. DLL stores the least significant part of the division.

Note that DLL and DLH can only be written to before sleep mode is enabled (i.e., before IER[4] is set).

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