Datasheet

TL16C752B
www.ti.com SLLS405C –DECEMBER 1999–REVISED JUNE 2010
PIN FUNCTIONS (continued)
PIN
I/O DESCRIPTION
NAME NO.
Read input (active low strobe). A high to low transition on IOR will load the contents of an internal register
IOR 19 I
defined by address bits A0-A2 onto the TL16C752B data bus (D0-D7) for access by an external CPU.
Write input (active low strobe). A low to high transition on IOW will transfer the contents of the data bus
IOW 15 I (D0-D7) from the external CPU to an internal register that is defined by address bits A0-A2 and CSA and
CSB.
User defined outputs. This function is associated with individual channels A and B. The state of these
pins is defined by the user through the software settings of the MCR register, bit 3. INTA-B are set to
OPA, OPB 32, 9 O active mode and OP to a logic 0 when the MCR-3 is set to a logic 1. INTA-B are set to the 3-state mode
and OP to a logic 1 when MCR-3 is set to a logic 0. See bit 3, modem control register (MCR bit 3). The
output of these two pins is high after reset.
Reset. RESET will reset the internal registers and all the outputs. The UART transmitter output and the
RESET 36 I receiver input will be disabled during reset time. See TL16C752B external reset conditions for initialization
details. RESET is an active-high input.
I Ring indicator (active low). These inputs are associated with individual UART channels A and B. A logic
low on these pins indicates the modem has received a ringing signal from the telephone line. A low to
RIA, RIB 41, 21 I
high transition on these input pins generates a modem status interrupt, if enabled. The state of these
inputs is reflected in the modem status register (MSR).
Request to send (active low). These outputs are associated with individual UART channels A and B. A
low on the RTS pin indicates the transmitter has data ready and waiting to send. Writing a 1 in the
RTSA, RTSB 33, 22 O modem control register (MCR bit 1) sets these pins to low, indicating data is available. After a reset, these
pins are set to high. These pins only affects the transmit and receive operation when auto RTS function is
enabled through the enhanced feature register (EFR) bit 6, for hardware flow control operation.
Receive data input. These inputs are associated with individual serial channel data to the 752B. During
RXA, RXB 5, 4 I the local loopback mode, these RX input pins are disabled and TX data is internally connected to the
UART RX input internally.
RXRDYA, Receive ready (active low). RXRDY A and B goes low when the trigger level has been reached or a
31, 18 O
RXRDYB timeout interrupt occurs. They go high when the RX FIFO is empty or there is an error in RX FIFO.
Transmit data. These outputs are associated with individual serial transmit channel data from the 752B.
TXA, TXB 7, 8 O During the local loopback mode, the TX input pin is disabled and TX data is internally connected to the
UART RX input.
TXRDYA, Transmit ready (active low). TXRDY A and B go low when there are at least a trigger level numbers of
43, 6 O
TXRDYB spaces available. They go high when the TX buffer is full.
V
CC
42 I Power supply inputs.
Crystal or external clock input. XTAL1 functions as a crystal input or as an external clock input. A crystal
XTAL1 13 I can be connected between XTAL1 and XTAL2 to form an internal oscillator circuit (see ). Alternatively, an
external clock can be connected to XTAL1 to provide custom data rates.
Output of the crystal oscillator or buffered clock. See also XTAL1. XTAL2 is used as a crystal oscillator
XTAL2 14 O
output or buffered a clock output.
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