Datasheet

TL16C752B
SLLS405C –DECEMBER 1999–REVISED JUNE 2010 www.ti.com
Table 8 lists and describes the TL16C752 internal registers.
Table 8. TL16C752A Internal Registers
(1)
Addr REGISTER BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 READ/ WRITE
000 RHR bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Read
000 THR bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Read
0/RTS Modem Rx data
0/CTS interrupt 0/Xoff sleep 0/X Sleep Rx line status THR empty
001 IER interrupt status available Read/Write
enable
(2)
mode
(2)
mode
(2)
interrupt interrupt
enable
(2)
interrupt interrupt
Rx trigger 0/TX trigger 0/TX trigger DMA mode Resets Tx
010 FCR Rx trigger level Resets Rx FIFO Enables FIFO Write
level level level select FIFO
0/CTS, Interrupt Interrupt Interrupt priority
010 IIR FCR(0) FCR(0) 0/Xoff
(2)
Interrupt status Read
RTS
(2)
priority Bit 2 priority Bit 1 Bit 0
DLAB and EFR Break control Parity type Parity No. of stop
011 LCR Sets parity Word length Word length Read/Write
enable bit select enable bits
TCR and TLR 0/Enable IRQ enable FIFO Rdy
100 MCR 1x or 1x/4 clock 0/Xon Any RTS DTR Read/Write
enable loopback OP enable
Parity
0/Error in Rx THR and TSR Break Framing
101 LSR THR empty Overrun error Data in receiver Read
FIFO empty interrupt error
error
110 MSR CD RI DSR CTS ΔCD ΔRI ΔDSR ΔCTS Read
111 SPR bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Read/Write
000 DLL bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Read/Write
001 DLH bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 Read/Write
Special Enable
S/W flow S/W flow S/W flow control S/W flow control
010 EFR Auto-CTS Auto-RTS character enhanced Read/Write
control Bit 3 control Bit 2 Bit 1 Bit 0
detect functions
(2)
100 Xon1 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Read/Write
101 Xon2 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Read/Write
110 Xoff1 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Read/Write
111 Xoff2 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Read/Write
010 TCE bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Read/Write
111 TLR bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Read/Write
RX FIFO B RX FIFO A TX FIFO B TX FIFO A
111 FIFORdy 0 0 0 0 Read
status status status status
(1) Refer to the notes under Table 7 for more register access information.
(2) The shaded bits in the above table can only be modified if register bit EFR[4] is enabled, i.e., if enhanced functions are enabled.
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