Datasheet
TXRDY (A–B)
IOW
Active
Byte32
D0–D7
TX(A–B)
Start
Bit
Stop
Bit
D0 D1 D2 D3 D4 D5 D6 D7
t
d18
t
d17
Trigger
Lead
Parity
Bit
T0477-01
5DataBits
6DataBits
7DataBits
DataBits(5–8)
TL16C752B
SLLS405C –DECEMBER 1999–REVISED JUNE 2010
www.ti.com
Figure 20. Transmit Ready Timing in FIFO Mode
TIMING ERROR CONDITION
Texas Instruments has discovered a timing anomaly in two of its newest products in the UART family, namely the
TL16C752 and TL16C752B.
The problem only occurs under a special set of circumstances (non-FIFO mode), and can be worked around by
using certain timing. Depending on actual system application, some customers may not see this problem. There
are currently no plans to fix this problem because it is felt that it is a minor issue. It is unlikely the device will be
used in non-FIFO mode, and if it is, the software workaround will not have a significant impact on throughput,
PROBLEM DESCRIPTION
When using the non-FIFO (single byte) mode of operation, it is possible that valid data could be reported as
available by either the line status register (LSR) or the interrupt identification register (IIR), before the receiver
holding register (RHR) can be read. In other words, the loading of valid data in RHR may be delayed when the
part operates in non-FIFO mode. The data in the RHr will be valid after a delay of one baud-clock period after the
update of the LSR or IIR. The baud-clock runs at 16X the baudrate. The following table is a sample of baud rates
and associated required delays. Depending on the operating environment, this time may well be transparent to
the system, e.g., less than the context switch time of the interrupt service routine.
A similar problem does not exist when using FIFO mode (64 byte) mode of operation.
BAUDRATE (BIT PER-SECOND) REQUIRED DELAY (µs)
1200 52.1 µs
2400 26 µs
4800 13 µs
9600 6.5 µs
19200 3.3 µs
38400 1.6 µs
57600 1.1 µs
115200 0.8 µs
1000000 62.5 ns
22 Submit Documentation Feedback Copyright © 1999–2010, Texas Instruments Incorporated
Product Folder Link(s): TL16C752B