Datasheet

TX(A–B)
INT (A–B)
IOW
Active
Active
Start
Bit
Stop
Bit
Parity
Bit
Next
Data
Start
Bit
Active
TxReady
t
d12
t
d14
t
d13
D0 D1 D2 D3 D4 D5 D6 D7
16BaudRateClock
T0475-01
DataBits(5–8)
5 Data Bits
6DataBits
7DataBits
TX(A–B)
TXRDY (A–B)
IOW
Active
Byte 1
D0–D7
D0 D1 D2 D3 D4 D5 D6 D7
Start
Bit
Stop
Bit
Parity
Bit
Transmitter
NotReady
Active
TransmitterReady
Next
Data
Start
Bit
t
d18
T0476-01
Data Bits (5–8)
t
d17
TL16C752B
www.ti.com SLLS405C –DECEMBER 1999–REVISED JUNE 2010
Figure 18. Transmit Timing
Figure 19. Transmit Ready Timing in Non-FIFO Mode
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Product Folder Link(s): TL16C752B