Datasheet

RX(A–B)
IOR
Active
Start
Bit
Stop
Bit
Parity
Bit
Next
Data
Start
Bit
xData
Ready
RXRDY (A–B)
RXRDY
D0
D1
D2
D3
D4 D5 D6 D7
t
d15
t
d16
T0473-01
Data Bits (5–8)
t
d16
RX(A–B)
IOR
Active
RXRDY
RXRDY
(A–B)
D0 D1 D2 D3 D4 D5 D6 D7
Start
Bit
Stop
Bit
Parity
Bit
FirstByte
ThatReaches
the Trigger
Level
Data
Ready
t
d15
T0474-01
DataBits(5–8)
TL16C752B
SLLS405C –DECEMBER 1999–REVISED JUNE 2010 www.ti.com
Figure 16. Receive Ready Timing in Non-FIFO Mode
Figure 17. Receive Timing in FIFO Mode
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