Datasheet

TL16C752B
www.ti.com SLLS405C –DECEMBER 1999–REVISED JUNE 2010
TIMING REQUIREMENTS
T
A
= –40°C to 85°C, V
CC
= 3.3 V ± 10% (unless otherwise noted) (see Figure 11–Figure 20)
PARAMETER TEST CONDITIONS MIN MAX UNIT
t
d1
IOR delay from chip select 0 ns
t
d2
Read cycle delay 2t
p(I)
(1)
ns
t
d3
Delay from IOR to data 28.5 ns
t
d4
Data disable time 15 ns
t
d5
IOW delay from chip select 10 ns
t
d6
Write cycle delay 2t
p(I)
(1)
ns
t
d7
Delay from IOW to output 100 pF load 50 ns
t
d8
Delay to set interrupt from MODEM input 100 pF load 70 ns
t
d9
Delay to reset interrupt from IOR 100 pF load 70 ns
t
d10
Delay from stop to set interrupt 1
Rclk
(2)
t
d11
Delay from IOR to reset interrupt 100 pF load 70 ns
t
d12
Delay from stop to interrupt 100 ns
t
d13
Delay from initial INT reset to transmit start 8 24
(2)
t
d14
Delay from IOW to reset interruptr 70 ns
t
d15
Delay from stop to set RXRDY 1 Clock
t
d16
Delay from IOR to reset RXRDY 1 µs
t
d17
Delay from IOW to set TXRDY 70 µs
t
d18
Delay from start to reset TXRDY 16
(2)
t
d19
Delay between successive assertion of IOW and IOR 4P
(1) (2)
t
h1
Chip select hold time from IOR 0 ns
t
h2
Chip select hold time from IOW 0 ns
t
h3
Data hold time 15 ns
t
h4
Address hold time 0 ns
t
h5
Hold time from XTAL1 clock ↓ to IOW or IOR release 20 ns
t
p1
, t
p2
Clock cycle period 20 ns
t
p3
Oscillator/clock speed V
CC
= 3 V 48 MHz
t
(RESET)
Reset pulse width 200 ns
t
su1
Address setup time 0 ns
t
su2
Data setup time 16 ns
t
su3
Setup time from IOW or IOR assertion to XTAL1 clock ↑ 20 ns
t
w1
IOR strobe width 2t
p(I)
(1)
ns
t
w2
IOW strobe width 2t
p(I)
(1)
ns
(1) t
p(I)
= input clock period
(2) Baud rate
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