Datasheet

TXRDY

wrptr

TXRDY

wrptr

FIFO Full

FIFOEmpty

RXRDY

rdptr

RXRDY

rdptr

Trigger

Level

Trigger

Level

AtLeastOne

LocationFilled

B0421-01

TL16C752B

SLLS405C –DECEMBER 1999–REVISED JUNE 2010

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Block DMA Transfers (DMA mode 1)

Transmitter: TXRDY is active when there is a trigger level number of spaces available. It becomes inactive

when the FIFO is full.

Receiver: RXRDY becomes active when the trigger level has been reached or when a timeout interrupt occurs.

It will go inactive when the FIFO is empty or an error in the RX FIFO is flagged by LSR(7).

Figure 8 shows TXRDY and RXRDY in DMA mode 1.

Figure 8. TXRDY and RXRDY in DMA Mode 1

Sleep Mode

Sleep mode is an enhanced feature of the TL16C752B UART. It is enabled when EFR[4], the enhanced

functions bit, is set AND when IER[4] is set. Sleep mode is entered when:

• The serial data input line, RX, is idle (see break and time-out conditions).

• The TX FIFO and TX shift register are empty.

• There are no interrupts pending except THR and time-out interrupts.

NOTE

Sleep mode will not be entered if there is data in the RX FIFO.

In sleep mode, the UART clock and baud rate clock are stopped. Since most registers are clocked using these

clocks, the power consumption is greatly reduced. The UART will wake up when any change is detected on the

RX line, when there is any change in the state of the modem input pins, or if data is written to the TX FIFO.

NOTE

Writing to the divisor latches, DLL and DLH, to set the baud clock, must not be done

during sleep mode. Therefore it is advisable to disable sleep mode using IER[4] before

writing to DLL or DLH.duced

Break and Timeout Conditions

An RX idle condition is detected when the receiver line, RX, has been high for a time equivalent to (4X

programmed word length)+12 bits. The receiver line is sampled midway through each bit.

When a break condition occurs the TX line is pulled low. A break condition is activated by setting LCR[6].

Product Folder Link(s): TL16C752B