Datasheet

0000
LSR
B0419-01
IER
RHRTHR
IOW/IOR
Processor
FIFO Empty
TXRDY
wrptr
TXRDY
wrptr
TX
B0420-01
FIFOEmpty
RXRDY
rdptr
RXRDY
rdptr
RX
AtLeastOne
LocationFilled
AtLeastOne
LocationFilled
TL16C752B
www.ti.com SLLS405C –DECEMBER 1999–REVISED JUNE 2010
Polled Mode Operation
In polled mode (IER[3:0]=0000) the status of the receiver and transmitter can be checked by polling the line
status register (LSR). This mode is an alternative to the FIFO interrupt mode of operation where the status of the
receiver and transmitter is automatically known by means of interrupts sent to the CPU. Figure 6 shows FIFO
polled mode operation.
Figure 6. FIFO Polled Mode Operation
DMA Signalling
There are two modes of DMA operation: DMA mode 0 or 1, selected by FCR[3].
In DMA mode 0 or FIFO disable (FCR[0]=0) DMA occurs in single character transfers. In DMA mode 1
multicharacter (or block) DMA transfers are managed to relieve the processor for longer periods of time.
Single DMA Transfers (DMA mode0/FIFO disable)
Transmitter: When empty, the TXRDY signal becomes active. TXRDY will go inactive after one character has
been loaded into it.
Receiver: RXRDY is active when there is at least one character in the FIFO. It becomes inactive when the
receiver is empty.
Figure 7 shows TXRDY and RXRDY in DMA mode0/FIFO disable.
Figure 7. TXRDY and RXRDY in DMA Mode 0/FIFO Disable
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