Datasheet

TL16C750
ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH 64-BYTE FIFOs AND AUTOFLOW CONTROL
SLLS191C – JANUARY 1995 – REVISED DECEMBER 1997
31
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
modem status register (MSR) (continued)
Bit 2: This bit is the trailing edge of the ring indicator (TERI) detector. TERI indicates that RI to the chip has
changed from a low to a high level. When TERI is set and the modem status interrupt is enabled, a modem
status interrupt is generated. When TERI is set, sleep or low-power modes are avoided.
Bit 3: This bit is the change in data carrier detect (∆DCD) indicator. ∆DCD indicates that DCD to the chip
has changed states since the last time it was read by the CPU. When ∆DCD is set and the modem status
interrupt is enabled, a modem status interrupt is generated. When ∆DCD is set, sleep or low-power modes
are avoided.
Bit 4: This bit is the complement of CTS. When the ACE is in the diagnostic test mode (LOOP
[MCR4] = 1), this bit is equal to the MCR bit 1 (RTS).
Bit 5: This bit is the complement of DSR input. When the ACE is in the diagnostic test mode (LOOP
[MCR4] = 1), this bit is equal to the MCR bit 0 (DTR).
Bit 6: This bit is the complement of RI. When the ACE is in the diagnostic test mode (LOOP [MCR4] = 1),
this bit is equal to the MCR bit 2 (OUT1).
Bit 7: This bit is the complement of DCD. When the ACE is in the diagnostic test mode (LOOP
[MCR4] = 1), this bit is equal to the MCR bit 3 (OUT2).
programmable baud generator
The ACE contains a programmable baud generator that takes a clock input in the range between dc and 16 MHz
and divides it by a divisor in the range between 1 and (2
16
–1). The output frequency of the baud generator is
16× the baud rate. The formula for the divisor is:
divisor = XIN frequency input ÷ (desired baud rate × 16)
Two 8-bit registers, called divisor latches, store the divisor in a 16-bit binary format. These divisor latches must
be loaded during initialization of the ACE to ensure desired operation of the baud generator. When either of the
divisor latches is loaded, a 16-bit baud counter is also loaded to prevent long counts on initial load.
Tables 9 and 10 illustrate the use of the baud generator with crystal frequencies of 1.8432 MHz and 3.072 MHz
respectively. For baud rates of 38.4 kbits/s and below, the error obtained is very small. The accuracy of the
selected baud rate is dependent on the selected crystal frequency (see Figure 21).