Datasheet

TL16C750
ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH 64-BYTE FIFOs AND AUTOFLOW CONTROL
SLLS191C – JANUARY 1995 – REVISED DECEMBER 1997
27
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
interrupt identification register (IIR) (continued)
Table 5. Interrupt Control Functions
INTERRUPT
IDENTIFICATION
REGISTER
PRIORITY
LEVEL
INTERRUPT TYPE INTERRUPT SOURCE
INTERRUPT RESET
METHOD
BIT 3 BIT 2 BIT 1 BIT 0
0 0 0 1 None None None None
0 1 1 0 1 Receiver line status
Overrun error, parity error,
framing error or break interrupt
Reading the line status register
0 1 0 0 2 Received data available
Receiver data available in the
TL16C450 mode or trigger level
reached in the FIFO mode.
Reading the receiver buffer
register
1 1 0 0 2
Character time-out
indication
No characters have been
removed from or input to the
receiver FIFO during the last
four character times, and there
is at least one character in it
during this time
Reading the receiver buffer
register
0 0 1 0 3
Transmitter holding
register empty
Transmitter holding register
empty
Reading the interrupt
identification register (if source
of interrupt) or writing into the
transmitter holding register
0 0 0 0 4 Modem status
Clear to send, data set ready,
ring indicator, or data carrier
detect
Reading the modem status
register
line control register (LCR)
The system programmer controls the format of the asynchronous data communication exchange through the
LCR. In addition, the programmer is able to retrieve, inspect, and modify the contents of the LCR; this eliminates
the need for separate storage of the line characteristics in system memory. The contents of this register are
summarized in Table 3 and described in the following bulleted list.
Bits 0 and 1: These two bits specify the number of bits in each transmitted or received serial character.
These bits are encoded as shown in Table 6.
Table 6. Serial Character Word Length
BIT 1 BIT 0 WORD LENGTH
0 0 5 bits
0 1 6 bits
1 0 7 bits
1 1 8 bits
Bit 2: This bit specifies either one, one and one-half, or two stop bits in each transmitted character. When
bit 2 is cleared, one stop bit is generated in the data. When bit 2 is set, the number of stop bits generated
is dependent on the word length selected with bits 0 and 1. The receiver clocks only the first stop bit,
regardless of the number of stop bits selected. The number of stop bits generated, in relation to word length
and bit 2, is shown in Table 7.