Datasheet
Bit
No.
TL16C750
ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH 64-BYTE FIFOs AND AUTOFLOW CONTROL
SLLS191C – JANUARY 1995 – REVISED DECEMBER 1997
23
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
accessible registers
The system programmer, through the CPU, has access to and control over any of the ACE registers. These
registers control ACE operations, receive data, and transmit data. Descriptions of these registers follow in
Table 3.
Table 3. Summary of Accessible Registers
REGISTER ADDRESS
0 DLAB = 0 0 DLAB = 0 1 DLAB = 0 2 2 3 4 5 6 7 0 DLAB = 1 1 DLAB = 1
Receiver
Buffer
Register
(Read
Only)
Transmitter
Holding
Register
(Write
Only)
Interrupt
Enable
Register
Interrupt
Ident.
Register
(Read
Only)
FIFO
Control
Register
(Write
Only)
Line
Control
Register
Modem
Control
Register
Line
Status
Register
Modem
Status
Register
Scratch
Register
Divisor
Latch
(LSB)
Latch
(MSB)
RBR THR IER IIR FCR LCR MCR LSR MSR SCR DLL DLM
0 Data Bit 0
†
Data Bit 0
Enable
Received
Data
Available
Interrupt
(ERBI)
0 when
interrupt
Pending
FIFO
Enable
Word
Length
Select
Bit 0
(WLS0)
Data
Terminal
Ready
(DTR)
Data
Ready
(DR)
Delta
Clear
to Send
(
∆CTS)
Bit 0 Bit 0 Bit 8
1 Data Bit 1 Data Bit 1
Enable
Transmitter
Holding
Register
Empty
Interrupt
(ETBEI)
Interrupt
ID
Bit 1
Receiver
FIFO
Reset
Word
Length
Select
Bit 1
(WLS1)
Request
to Send
(RTS)
Overrun
Error
(OE)
Delta
Data
Set
Ready
(
∆DSR)
Bit 1 Bit 1 Bit 9
2 Data Bit 2 Data Bit 2
Enable
Receiver
Line Status
Interrupt
(ELSI)
Interrupt
ID
Bit 2
Transmitter
FIFO
Reset
Number
of
Stop Bits
(STB)
OUT1
Parity
Error
(PE)
Trailing
Edge Ring
Indicator
(TERI)
Bit 2 Bit 2 Bit 10
3 Data Bit 3 Data Bit 3
Enable
Modem
Status
Interrupt
(EDSSI)
Interrupt
ID
Bit 2
(see
Note 4)
DMA
Mode
Select
Parity
Enable
(PEN)
OUT2
Framing
Error
(FE)
Delta
Data
Carrier
Detect
(
∆DCD)
Bit 3 Bit 3 Bit 11
4 Data Bit 4 Data Bit 4
Sleep Mode
Enable
0 Reserved
Even
Parity
Select
(EPS)
Loop
Break
Interrupt
(BI)
Clear
to
Send
(CTS)
Bit 4 Bit 4 Bit 12
5 Data Bit 5 Data Bit 5
Low Power
Mode Enable
64 Byte
FIFO
Enabled
64 Byte
FIFO
Enable
‡
Stick
Parity
Flow
Control
Enable
(AFE)
Transmitter
Holding
Register
(THRE)
Data
Set
Ready
(DSR)
Bit 5 Bit 5 Bit 13
6 Data Bit 6 Data Bit 6 0
FIFOs
Enabled
(see
Note 11)
Receiver
Trigger
(LSB)
Break
Control
0
Transmitter
Empty
(TEMT)
Ring
Indicator
(RI)
Bit 6 Bit 6 Bit 14
7 Data Bit 7 Data Bit 7 0
FIFOs
Enabled
(see
Note 11)
Receiver
Trigger
(MSB)
Divisor
Latch
Access
Bit
(DLAB)
‡
0
Error in
Receiver
FIFO
(see
Note 12)
Data
Carrier
Detect
(DCD)
Bit 7 Bit 7 Bit 15
†
Bit 0 is the least significant bit. It is the first bit serially transmitted or received.
‡
Access to DLAB LSB, MSB, and FCR bit 5 require LCR bit 7 = 1
NOTE 11: These bits are always 0 in the TL16C450 mode.