Datasheet

TL16C750
ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH 64-BYTE FIFOs AND AUTOFLOW CONTROL
SLLS191C – JANUARY 1995 – REVISED DECEMBER 1997
22
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
Table 1. Register Selection
DLAB
†
A2 A1 A0 REGISTER
0 L L L Receiver buffer (read), transmitter holding register (write)
0 L L H Interrupt enable register
X L H L Interrupt identification register (read only)
X L H L FIFO control register (write)
X L H H Line control register
X H L L Modem control register
X H L H Line status register
X H H L Modem status register
X H H H Scratch register
1 L L L Divisor latch (LSB)
1 L L H Divisor latch (MSB)
†
The divisor latch access bit (DLAB) is the most significant bit of the line control register. The DLAB signal
is controlled by writing to this bit location (see Table 3).
Table 2. ACE Reset Functions
REGISTER/SIGNAL
RESET
CONTROL
RESET STATE
Interrupt Enable Register Master Reset All bits cleared (0–5 forced and 6–7 permanent)
Interrupt Identification Register Master Reset Bit 0 is set, bits 1–4 are cleared, and bits 5–7 are cleared
FIFO Control Register Master Reset All bits cleared
Line Control Register Master Reset All bits cleared
Modem Control Register Master Reset All bits cleared (6–7 permanent)
Line Status Register Master Reset Bits 5 and 6 are set, all other bits are cleared
Modem Status Register Master Reset Bits 0–3 are cleared, bits 4–7 are input signals
SOUT Master Reset High
INTRPT (receiver error flag) Read LSR/MR Low
INTRPT (received data available) Read RBR/MR Low
INTRPT (transmitter holding register empty) Read IR/Write THR/MR Low
INTRPT (modem status changes) Read MSR/MR Low
OUT2 Master Reset High
RTS Master Reset High
DTR Master Reset High
OUT1 Master Reset High
Scratch Register Master Reset No effect
Divisor Latch (LSB and MSB) Registers Master Reset No effect
Receiver Buffer Registers Master Reset No effect
Transmitter Holding Registers Master Reset No effect
Receiver FIFO
MR/FCR1–FCR0/
∆FCR0
All bits cleared
XMIT FIFO
MR/FCR2–FCR0/
∆FCR0
All bits cleared