Datasheet

TL16C750
ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH 64-BYTE FIFOs AND AUTOFLOW CONTROL
SLLS191C – JANUARY 1995 – REVISED DECEMBER 1997
20
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
D7–D0
MEMR
or I/OR
MEMW or I/ON
INTR
RESET
A0
A1
A2
CS
L
H
EIA
232-D Drivers
and Receivers
XOUT
XIN
RCLK
BAUDOUT
RI
CTS
DCD
DSR
DTR
RTS
SOUT
SIN
INTRPT
D7–D0
RD
1
WR
1
MR
A0
A1
A2
ADS
WR2
RD2
CS2
CS1
CS0
TL16C750
(ACE)
3.072 MHz
C
P
U
B
U
S
Figure 18. Basic TL16C750 Configuration
APPLICATION INFORMATION
Receiver Disable
Microcomputer
System
Data Bus Data Bus
Driver Disable
8-Bit
Bus Transceiver
WR
WR1
D7–D0
DDIS
TL16C750
(ACE)
Figure 19. Typical Interface for a High-Capacity Data Bus