Datasheet

TL16C750
ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH 64-BYTE FIFOs AND AUTOFLOW CONTROL
SLLS191C – JANUARY 1995 – REVISED DECEMBER 1997
15
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
t
d13
Active
Active
RD1
, RD2
(read RBR)
RCLK
t
d14
8 Clocks
t
d12
Parity StopStart Data Bits 5–8
Sample Clock
TL16C450 Mode:
Sample Clock
SIN
INTRPT
(data ready)
INTRPT
(receiver error)
RD1
, RD2
(read LSR)
50%50%
50%
50%
50%
50%
t
d14
Figure 7. Receiver Timing Waveforms