Datasheet

TL16C750
ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH 64-BYTE FIFOs AND AUTOFLOW CONTROL
SLLS191C – JANUARY 1995 – REVISED DECEMBER 1997
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
commercial maximum switching characteristics, V
CC
= 4.75 V, T
J
= 115°C
PARAMETER
FROM TO
INTRINSIC
DELAY
DELTA
DELAY
DELAY (ns)
PARAMETER
(INPUT) (OUTPUT)
DELAY
(ns)
DELAY
(ns/pF)
C
L
= 15 pF C
L
= 50 pF C
L
= 85 pF C
L
= 100 pF
t
PLH
XIN
XO
–0.92 0.571 7.65 27.66 47.66 56.23
t
PHL
XIN
XO
–0.79 0.312 3.89 14.83 25.76 30.45
t
r
Output rise time, XO 10.86 40.42 69.98 82.65
t
f
Output fall time, XO 5.47 20.90 36.34 42.95
commercial maximum switching characteristics, V
CC
= 3 V, T
J
= 115°C
PARAMETER
FROM TO
INTRINSIC
DELAY
DELTA
DELAY
DELAY (ns)
PARAMETER
(INPUT) (OUTPUT)
DELAY
(ns)
DELAY
(ns/pF)
C
L
= 15 pF C
L
= 50 pF C
L
= 85 pF C
L
= 100 pF
t
PLH
XIN
XO
–4.69 1.017 10.57 46.16 81.75 97.00
t
PHL
XIN
XO
–3.05 0.442 3.58 19.04 34.51 41.13
t
r
Output rise time, XO 14.39 64.87 115.35 136.98
t
f
Output fall time, XO 5.06 26.53 48.01 57.21
receiver switching characteristics over recommended ranges of supply voltage and operating
free-air temperature (see Note 10)
PARAMETER ALT. SYMBOL FIGURE TEST CONDITIONS MIN MAX UNIT
t
d12
Delay time, RCLK to sample clock t
SCD
7 10 ns
t
d13
Delay time, stop to set receiver error inter-
rupt or read RBR to LSI interrupt or stop to
RXRDY
↓
t
SINT
7, 8, 9,
10, 11
2
RCLK
cycle
t
d14
Delay time, read RBR/LSR low to reset
interrupt low
t
RINT
7, 8, 9,
10, 11
C
L
= 75 pF 120 ns
NOTE 10: In the FIFO mode, the read cycle (RC) = 425 ns (minimum) between reads of the receive FIFO and the status registers (interrupt
identification register or line status register).
transmitter switching characteristics over recommended ranges of supply voltage and operating
free-air temperature
PARAMETER
†
ALT. SYMBOL FIGURE TEST CONDITIONS MIN MAX UNIT
t
d15
Delay time, INTRPT to transmit start t
IRS
12 8 24
baudout
cycles
t
d16
Delay time, start to interrupt t
STI
12 8 10
baudout
cycles
t
d17
Delay time, WR THR to reset interrupt t
HR
12 C
L
= 75 pF 50 ns
t
d18
Delay time, initial write to interrupt (THRE) t
SI
12 16 34
baudout
cycles
t
d19
Delay time, read IIR to reset interrupt (THRE) t
IR
12 C
L
= 75 pF 70 ns
t
d20
Delay time, write to TXRDY inactive t
WXI
13, 14 C
L
= 75 pF 75 ns
t
d21
Delay time, start to TXRDY active
t
SXA
13, 14 C
L
= 75 pF 9
baudout
cycles
†
THRE = transmitter holding register empty, IIR = interrupt identification register.