Datasheet

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  
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SLLS165G − JANUARY 1994 − REVISED MARCH 2006
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
functional block diagram
†
TL16C550B
Circuitry
TL16C550B
Circuitry
TL16C550B
Circuitry
TL16C550B
Circuitry
Receive
Control
Logic
Transmit
Control
Logic
Modem
Control
Logic
Control
Logic
Data
Bus
Clock
Circuit
RXx
TXx
CTSx
RTSx
DSRx
DTRx
RIx
DCDx
D7−D0
A2−A0
CSx
IOR, IOW
RESET
XTAL1
XTAL2
INTx
TXRDY
, RXRDY
Interrupt
Logic
8
†
For TL16C550 circuitry, refer to the TL16C550B data sheet.
Terminal Functions
TERMINAL
NAME
FN
NO.
PN
NO.
I/O
DESCRIPTION
A0
A1
A2
34
33
32
48
47
46
I Register select terminals. A0, A1, and A2 are three inputs used during read and write operations to
select the ACE register to read or write.
CSA, CSB,
CSC
, CSD
16, 20,
50, 54
28, 33,
68, 73
I Chip select. Each chip select (CSx) enables read and write operations to its respective channel.
CTSA, CTSB,
CTSC
, CTSD
11, 25,
45, 59
23, 38,
63, 78
I Clear to send. CTSx is a modem status signal. Its condition can be checked by reading bit 4 (CTS)
of the modem status register. CTS
has no affect on the transmit or receive operation.
D7−D0 66−68
1−5
15−11,
9−7
I/O Data bus. Eight data lines with 3-state outputs provide a bidirectional path for data, control, and status
information between the TL16C554 and the CPU. D0 is the least significant bit (LSB).
DCDA, DCDB,
DCDC
, DCDD
9, 27,
43, 61
19,42,
59, 2
I Data carrier detect. A low on DCDx indicates the carrier has been detected by the modem. The
condition of this signal is checked by reading bit 7 of the modem status register.
DSRA, DSRB,
DSRC
, DSRD
10, 26,
44, 60
22, 39,
62, 79
I
Data set ready. DSRx is a modem status signal. Its condition can be checked by reading bit 5 (DSR)
of the modem status register. DSR
has no affect on the transmit or receive operation.
DTRA, DTRB,
DTRC
, DTRD
12, 24,
46, 58
24, 37,
64, 77
O Data terminal ready. DTRx is an output that indicates to a modem or data set that the ACE is ready
to establish communications. It is placed in the active state by setting the DTR bit of the modem
control register. DTRx is placed in the inactive state (high) either as a result of the master reset during
loop mode operation or clearing bit 0 (DTR
) of the modem control register.
GND 6, 23,
40, 57
16, 36,
56, 76
Signal and power ground
INTN
65 6 I
Interrupt normal. INTN operates in conjunction with bit 3 of the modem status register and affects
operation of the interrupts (INTA, INTB, INTC, and INTD) for the four universal asynchronous
receiver/transceivers (UARTs) per the following table.
INTN OPERATION OF INTERRUPTS
Brought low or
allowed to float
Interrupts are enabled according to the state of OUT2 (MCR bit 3). When the MCR
bit 3 is cleared, the 3-state interrupt output of that UART is in the high-impedance
state. When the MCR bit 3 is set, the interrupt output of the UART is enabled.
Brought high Interrupts are always enabled, overriding the OUT2 enables.