Datasheet
SLLS165G − JANUARY 1994 − REVISED MARCH 2006
29
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
reset
After power up, the ACE RESET input should be held high for one microsecond to reset the ACE circuits to an
idle mode until initialization. A high on RESET causes the following:
1. It initializes the transmitter and receiver internal clock counters.
2. It clears the LSR, except for transmitter register empty (TEMT) and transmit holding register empty (THRE),
which are set. The MCR is also cleared. All of the discrete lines, memory elements, and miscellaneous logic
associated with these register bits are also cleared or turned off. The LCR, divisor latches, RBR, and
transmitter buffer register are not affected.
RXRDY operation
In mode 0, RXRDY is asserted (low) when the receive FIFO is not empty; it is released (high) when the FIFO
is empty. In this way, the receiver FIFO is read when RXRDY
is asserted (low).
In mode 1, RXRDY
is asserted (low) when the receive FIFO has filled to the trigger level or a character time-out
has occurred (four character times with no transmission of characters); it is released (high) when the FIFO is
empty. In this mode, multiple received characters are read by the DMA device, reducing the number of times
it is interrupted.
RXRDY
and TXRDY outputs from each of the four internal ACEs of the TL16C554 are ANDed together
internally. This combined signal is brought out externally to RXRDY
and TXRDY.
Following the removal of the reset condition (RESET low), the ACE remains in the idle mode until programmed.
A hardware reset of the ACE sets the THRE and TEMT status bits in the LSR. When interrupts are subsequently
enabled, an interrupt occurs due to THRE. A summary of the effect of a reset on the ACE is given in Table 12.
Table 12. RESET Affects on Registers and Signals
REGISTER/SIGNAL RESET CONTROL RESET STATE
Interrupt enable register Reset All bits cleared (0−3 forced and 4−7 permanent)
Interrupt identification register Reset
Bit 0 is set, bits 1, 2, 3, 6, and 7 are cleared,
Bits 4−5 are permanently cleared
Line control register Reset All bits cleared
Modem control register Reset All bits cleared (5−7 permanent)
FIFO control register Reset All bits cleared
Line status register Reset All bits cleared, except bits 5 and 6 are set
Modem status register Reset Bits 0−3 cleared, bits 4−7 input signals
TXx Reset High
Interrupt (RCVR ERRS) Read LSR/Reset Low
Interrupt (receiver data ready) Read RBR/Reset Low
Interrupt (THRE) Read IIR/Write THR/Reset Low
Interrupt (modem status changes) Read MSR/Reset Low
RTS
Reset High
DTR
Reset High