Datasheet
SLLS165G − JANUARY 1994 − REVISED MARCH 2006
25
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
modem status register (MSR) (continued)
Table 7. Modem Status Register BIts
MSR BIT MNEMONIC DESCRIPTION
MSR0 ∆CTS Delta clear to send
MSR1 ∆DSR Delta data set ready
MSR2 TERI Trailing edge of ring indicator
MSR3 ∆DCD Delta data carrier detect
MSR4 CTS Clear to send
MSR5 DSR Data set ready
MSR6 RI Ring indicator
MSR7 DCD Data carrier detect
programming
The serial channel of the ACE is programmed by the control registers LCR, IER, DLL, DLM, MCR, and FCR.
These control words define the character length, number of stop bits, parity, baud rate, and modem interface.
While the control registers can be written in any order, the IER should be written last because it controls the
interrupt enables. Once the serial channel is programmed and operational, these registers can be updated any
time the ACE serial channel is not transmitting or receiving data.
programmable baud rate generator
The ACE serial channel contains a programmable baud rate generator (BRG) that divides the clock (dc to
8 MHz) by any divisor from 1 to (2
16
−1). Two 8-bit divisor latch registers store the divisor in a 16-bit binary
format. These divisor latch registers must be loaded during initialization. Upon loading either of the divisor
latches, a 16-bit baud counter is immediately loaded. This prevents long counts on initial load. The BRG can
use any of three different popular frequencies to provide standard baud rates. These frequencies are 1.8432
MHz, 3.072 MHz, and 8 MHz. With these frequencies, standard bit rates from 50 kbps to 512 kbps are available.
Tables 8, 9, 10, and 11 illustrate the divisors needed to obtain standard rates using these three frequencies. The
output frequency of the baud rate generator is 16× the data rate [divisor # = clock + (baud rate × 16)] referred
to in this document as RCLK.