Datasheet

 
  


SLLS165G − JANUARY 1994 − REVISED MARCH 2006
13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
Stop
t
d9
(see Note A)
t
pd4
Top Byte of FIFO
t
pd4
t
d9
Active Active
Sample
Clock
INTx
(time-out or
trigger level)
Interrupt
IOR
(RD RBR)
IOR
(RD LSR)
Previous BYTE
Read From FIFO
Active
(FIFO at or above
trigger level)
(FIFO below
trigger level)
RXx
INTx
Interrupt
50%50%
50%
50% 50%
50%
50%
NOTE A: This is the reading of the last byte in the FIFO.
Figure 11. Receiver FIFO After First Byte (After RDR Set) Waveforms

  



  



 



RXx
50%
50%
50%
NOTES: A. This is the reading of the last byte in the FIFO.
B. If FCR0 = 1, then t
d9
= 3 RCLK cycles. For a time-out interrupt, t
d9
= 8 RCLK cycles.
Figure 12. Receiver Ready Mode 0 Timing Waveforms