Datasheet

TL16C554A, TL16C554AI
ASYNCHRONOUS-COMMUNICATIONS ELEMENT


SLLS509E − AUGUST 2001 − REVISED JUNE 2010
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
functional block diagram (per channel)
Receiver
Buffer
Register
Divisor
Latch (LS)
Divisor
Latch (MS)
Baud
Generator
Receiver
FIFO
Line
Status
Register
Transmitter
Holding
Register
Modem
Control
Register
Modem
Status
Register
Line
Control
Register
Transmitter
FIFO
Interrupt
Enable
Register
Interrupt
Identification
Register
FIFO
Control
Register
Select
and
Control
Logic
Interrupt
Control
Logic
S
e
l
e
c
t
Data
Bus
Buffer
RXA
TXA
CTSA
DTRA
DSRA
DCDA
RIA
INTA
11
12
10
9
8
15
17
7
16
A0
34
D(7 −0)
5 − 66
Internal
Data
Bus
33
32
20
50
54
37
52
18
39
35
36
38
65
A1
A2
CSA
CSB
CSC
CSD
RESET
IOR
IOW
XTAL1
RXRDY
S
e
l
e
c
t
Receiver
Shift
Register
Receiver
Timing and
Control
Transmitter
Timing and
Control
Transmitter
Shift
Register
Modem
Control
Logic
8
13, 30, 47, 64
6, 23, 40, 57
V
CC
GND
Power
Supply
RTSA
14
Autoflow
Control
(AFE)
8
8
8
8
8
8
8
TXRDY
XTAL2
INTN
NOTE A: Terminal numbers shown are for the FN package and channel A.