Datasheet

TL16C554A, TL16C554AI
ASYNCHRONOUS-COMMUNICATIONS ELEMENT
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SLLS509E − AUGUST 2001 − REVISED JUNE 2010
28
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
modem-control register (MCR) (continued)
D Bit 6 − Bit 7: MCR5, MCR6, and MCR7 are permanently cleared.
Data Terminal
Ready
0 = DTR Output Inactive (high)
1 = DTR
Output Active (low)
MODEM CONTROL REGISTER
MCR
7
MCR
6
MCR
5
MCR
4
MCR
3
MCR
2
Loop
0 = Loop Disabled
1 = Loop Enabled
Bits Are Set to Logic 0
Request
to Send
0 = RTS
Output Inactive (high)
1 = RTS
Output Active (low)
MCR
1
MCR
0
Out1 (internal)
Out2 (internal)
No effect on external operation
0 = External Interrupt Disabled
1 = External Interrupt Enabled
AFE
0 = AFE Disabled
1 = AFE Enabled
Figure 19. Modem-Control Register Contents
modem-status register (MSR)
The MSR provides the CPU with status of the modem input lines for the modem or peripheral devices. The MSR
allows the CPU to read the serial channel modem signal inputs by accessing the data bus interface of the ACE.
It also reads the current status of four bits of the MSR that indicate whether the modem inputs have changed
since the last reading of the MSR. The delta status bits are set when a control input from the modem changes
states, and are cleared when the CPU reads the MSR.
The modem input lines are CTS
, DSR, RI, and DCD. MSR4 − MSR7 are status indicators of these lines. A status
bit = 1 indicates the input is low. When the status bit is cleared, the input is high. When the modem-status
interrupt in the IER is enabled (IIR3 is set), an interrupt is generated whenever any one of MSR0 − MSR3 is set,
except as noted below in the delta CTS
description. The MSR is a priority 4 interrupt. The contents of the MSR
are described in Table 8.
D Bit 0: MSR0 is the delta clear-to-send (ΔCTS) bit. ΔCTS indicates that the CTS input to the serial channel
has changed state since it was last read by the CPU. No interrupt will be generated if auto-CTS
mode is
enabled.
D Bit 1: MSR1 is the delta data set ready (ΔDSR) bit. ΔDSR indicates that the DSR input to the serial channel
has changed states since the last time it was read by the CPU.
D Bit 2: MSR2 is the trailing edge of ring indicator (TERI) bit. TERI indicates that the RI input to the serial
channel has changed states from low to high since the last time it was read by the CPU. High-to-low
transitions on RI do not activate TERI.
D Bit 3: MSR3 is the delta data carrier detect (ΔDCD) bit. ΔDCD indicates that the DCD input to the serial
channel has changed states since the last time it was read by the CPU.
D Bit 4: MSR4 is the clear-to-send (CTS) bit. CTS is the complement of the CTS input from the modem
indicating to the serial channel that the modem is ready to receive data from SOUT. When the serial channel
is in the loop mode (MCR4 = 1), MSR4 reflects the value of RTS in the MCR.
D Bit 5: MSR5 is the data set ready DSR bit. DSR is the complement of the DSR input from the modem to
the serial channel that indicates that the modem is ready to provide received data from the serial channel
receiver circuitry. When the channel is in the loop mode (MCR4 is set), MSR5 reflects the value of DTR in
the MCR.