Datasheet

TL16C554A, TL16C554AI
ASYNCHRONOUS-COMMUNICATIONS ELEMENT


SLLS509E − AUGUST 2001 − REVISED JUNE 2010
15
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
t
pd4
Parity StopStart Data Bits (5 −8)
TL16C450 Mode:
Sample Clock
SIN
(receiver input data)
INTx
(data ready or
RCVR ERR)
IOR
t
d9
Active
50% 50%
50%
Figure 9. Receiver Timing Waveforms
Start
Data Bits (5 −8) Parity
Stop
Sample
Clock
t
d9
t
pd4
INTx (trigger
interrupt)
(FCR6, 7 = 0, 0)
(FIFO at or
above trigger
level)
(FIFO below
trigger level)
Active
IOR
(RD RBR)
IOR
(RD LSR)
t
pd4
Active
RXx
LSR
Interrupt
50%50%
50%
50%50%
50%
Figure 10. Receiver FIFO First Byte (Sets RDR) Waveforms