Datasheet
SLLS102B − DECEMBER 1990 − REVISED MARCH 1996
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251−1443
PARAMETER MEASUREMENT INFORMATION
2 V
0.8 V
CLK (XTAL1)
t
w1
t
w2
f
clock
= 8 MHz MAX
Figure 1. Clock Input (CLK) Voltage Waveform
Device Under Test
680 Ω
82 pF
†
2.54 V
TL16C552
†
Includes scope and jig capacitance
Figure 2. Output Load Circuit
Option
Jumpers
Data Bus
Address Bus
Control Bus
9-Pin D Connector
9-Pin D Connector
25-Pin D Connector
Serial
Channel 1
Buffers
Serial
Channel 2
Buffers
Parallel
Port
R/C
Network
Dual
Ace and
Printer
Port
TL16C552
Figure 3. Basic Test Configuration