Datasheet
SLLS102B − DECEMBER 1990 − REVISED MARCH 1996
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251−1443
electrical characteristics over recommended ranges of operating free-air temperature and supply
voltage
PARAMETER TEST CONDITIONS MIN MAX UNIT
V
OH
High-level output voltage
I
OH
= −0.4 mA for DB0−DB7,
I
OH
= −2 mA for PD0−PD7,
I
OH
= −0.4 mA for INIT
, AFD, STB, and SLIN (see Note 2),
I
OH
= −0.4 mA for all other outputs
2.4 V
V
OL
Low-level output voltage
I
OL
= 4 mA for DB0−DB7,
I
OL
= 12 mA for PD0−PD7,
I
OL
= 10 mA for INIT, AFD, STB, and SLIN (see Note 2),
I
OL
= 2 mA for all other outputs
0.4 V
I
I
Input current V
DD
= 5.25 V, All other terminals are floating ± 10 µA
I
I(CLK)
Clock input current V
I
= 0 to 5.25 V ± 10 µA
V
DD
= 5.25 V, V
O
= 0 with chip deselected, or
I
OZ
High-impedance output current
V
DD
= 5.25 V, V
O
= 0 with chip deselected, or
V
O
= 5.25 V with chip and write mode selected
± 20
µA
I
OZ
High-impedance output current
DD O
V
O
= 5.25 V with chip and write mode selected
± 20
µA
V
DD
= 5.25 V, No loads on outputs,
I
DD
Supply current
V
DD
= 5.25 V, No loads on outputs,
SIN0, SIN1, DSR0, DSR1, DCD0, DCD1, CTS0, CTS1,
50
mA
I
DD
Supply current
SIN0, SIN1, DSR0, DSR1, DCD0, DCD1, CTS0, CTS1,
RI0 and RI1 at 2 V, Other inputs at 0.8 V,
50
mA
RI0 and RI1 at 2 V, Other inputs at 0.8 V,
Baud rate generator f
clock
= 8 MHz, Baud rate = 56 kbit/s
NOTE 2: These four terminals contain an internal pullup resistor to V
DD
of approximately 10 kΩ.
clock timing requirements over recommended ranges of operating free-air temperature and supply
voltage
MIN MAX UNIT
t
w1
Pulse duration, CLK high (external clock, 8 MHz max) (see Figure 1) 55 ns
t
w2
Pulse duration, CLK low (external clock, 8 MHz max) (see Figure 1) 55 ns
t
w3
Pulse duration, master (RESET) low (see Figure 16) 1000 ns
read cycle timing requirements over recommended ranges of operating free-air temperature and
supply voltage (see Figure 4)
MIN MAX UNIT
t
w4
Pulse duration, IOR low 80 ns
t
su1
Setup time, chip select valid before IOR low (see Note 3) 15 ns
t
su2
Setup time, A2−A0 valid before IOR low (see Note 3) 15 ns
t
h1
Hold time, A2−A0 valid after IOR high (see Note 3) 20 ns
t
h2
Hold time, chip select valid after IOR high (see Note 3) 20 ns
t
d1
Delay time, t
su2
+ t
w4
+ t
d2
(see Note 4) 175 ns
t
d2
Delay time, IOR high to IOR or IOW low 80 ns
NOTES: 3. The internal address strobe is always active.
4. In the FIFO mode, t
d1
= 425 ns (min) between reads of the receiver FIFO and the status registers (IIR and LSR).