Datasheet
SLLS102B − DECEMBER 1990 − REVISED MARCH 1996
26
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251−1443
PRINCIPLES OF OPERATION
master reset
After power up, the ACE RESET input should be held low for one microsecond to reset the ACE circuits to an
idle mode until initialization. A low on RESET
causes the following:
1. It initializes the transmitter and receiver clock counters.
2. It clears the LSR, except for TEMT and THRE, which are set. The MCR is also cleared. All of the discrete
lines, memory elements, and miscellaneous logic associated with these register bits are also cleared or
turned off. The LCR, divisor latches, RBR, and transmitter buffer register are not effected.
Following the removal of the reset condition (RESET high), the ACE remains in the idle mode until programmed.
A hardware reset of the ACE sets the THRE and TEMT status bit in the LSR. When interrupts are subsequently
enabled, an interrupt occurs due to THRE. A summary of the affect of a reset on the ACE is given in Table 10.
Table 10. RESET
Affects On Registers and Signals
REGISTER/SIGNAL RESET CONTROL RESET
Interrupt enable register Reset
All bits cleared (0−3 forced and 4−7
permanent)
Interrupt identification register
Reset
Bit 0 is set, bits 1, 2, 3, 6, and 7 cleared
Interrupt identification register Reset
Bit 0 is set, bits 1, 2, 3, 6, and 7 cleared
Bits 4−5 are permanently cleared
Line control register Reset All bits cleared
Modem control register Reset All bits cleared
FIFO control register Reset All bits cleared
Line status register Reset All bits cleared, except bits 5 and 6 are set
Modem status register Reset Bits 0−3 cleared, bits 4−7 input signal
SOUT Reset High
Interrupt (receiver errs) Read LSR/Reset Cleared
Interrupt (receiver data ready) Read RBR/Reset Cleared
Interrupt (THRE) Read IIR/Write THR/Reset Cleared
Interrupt (modem status changes) Read MSR/Reset Cleared
OUT2
Reset High
RTS
Reset High
DTR
Reset High
OUT1
Reset High