Datasheet

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SLLS102B − DECEMBER 1990 − REVISED MARCH 1996
20
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251−1443
PRINCIPLES OF OPERATION
interrupt enable register (IER) (continued)
D Bit 1: IER1, when set, enables the THRE interrupt.
D Bit 2: IER2, when set, enables the receiver line status interrupt.
D Bit 3: IER3, when set, enables the modem status interrupt.
D Bits 4 − 7: IER4 − IER7 are always cleared.
interrupt identification register (IIR)
In order to minimize software overhead during data character transfers, the serial channel prioritizes interrupts
into four levels. The four levels of interrupt conditions are shown in the following bulleted list:
D Priority 1 − Receiver line status (highest priority)
D Priority 2 − Receiver data ready or receiver character time out
D Priority 3 −Transmitter holding register empty
D Priority 4−Modem status (lowest priority)
Information indicating that a prioritized interrupt is pending and the type of interrupt is stored in the IIR. The IIR
indicates the highest priority interrupt pending. The contents of the IIR are indicated in Table 5.
Table 5. Interrupt Control Functions
FIFO
MODE
ONLY
INTERRUPT
IDENTIFICATION
REGISTER
INTERRUPT SET AND RESET FUNCTIONS
BIT 3 BIT 2 BIT 1 BIT 0
PRIORITY
LEVEL
INTERRUPT TYPE INTERRUPT SOURCE
INTERRUPT RESET
CONTROL
0 0 0 1 − None None −
0 1 1 0 First Receiver line status OE, PE, FE, or BI LSR read
0 1 0 0 Second Received data available Receiver data available or trigger level
reached
RBR read until FIFO
drops below the
trigger level
1 1 0 0 Second Character time-out
indication
No characters have been removed
from or input to the receiver FIFO
during the last four character times and
there is at least one character in it
during this time.
RBR read
0 0 1 0 Third THRE THRE IIR read if THRE is
the interrupt source
or THR write
0 0 0 0 Fourth Modem status CTS, DSR, RI, or DCD MSR read
D Bit 0: IIR0 indicates whether an interrupt is pending. When IIR0 is cleared, an interrupt is pending.
D Bits 1 and 2: IIR1 and IIR2 identify the highest priority interrupt pending as indicated in Table 5.
D Bit 3: IIR3 is always cleared when in the TL16C450 mode. This bit is set along with bit 2 when in the FIFO
mode and a trigger change level interrupt is pending.
D Bits 4 and 5: IIR4 and IIR5 are always cleared.
D Bits 6 and 7: IIR6 and IIR7 are set when FCR0=1.