Datasheet


   
 
SLLS102B − DECEMBER 1990 − REVISED MARCH 1996
2
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251−1443
description (continued)
received from peripheral devices or modems and parallel-to-serial conversion on data characters transmitted
by the CPU. The complete status of each channel of the dual ACE can be read at any time during functional
operation by the CPU. The information obtained includes the type and condition of the transfer operations being
performed and the error conditions.
In addition to its dual communications interface capabilities, the TL16C552 provides the user with a fully
bidirectional parallel data port that fully supports the parallel Centronics-type printer. The parallel port and the
two serial ports provide IBM PC/AT-compatible computers with a single device to serve the three system ports.
A programmable baud rate generator is included that can divide the timing reference clock input by a divisor
between 1 and (2
16
− 1).
The TL16C552 is housed in a 68-pin plastic leaded chip carrier.
functional block diagram
CTS0
DSR0
DCD0
RI0
SIN0
CS0
DBDB7
RTS0
DTR0
SOUT0
INT0
RXRDY0
TXRDY0
RTS1
DTR1
SOUT1
INT1
RXRDY1
TXRDY1
BDO
24
25
26
45
9
22
12
11
10
60
61
42
5346
57
56
55
58
59
CTS1
DSR1
DCD1
RI1
SIN1
CS1
28
31
29
30
41
32
1421 8
8
13
5
8
6
62
3
36
37
39
4
A0A2
IOW
IOR
RESET
CLK
ERR
SLCT
BUSY
PE
ACK
PEMD
CS2
ENIRQ
63
65
66
67
68
1
38
43
8
8
PD0PD7
INIT
AFD
STB
SLIN
INT2
44
Select
and
Control
Logic
Parallel
Port
ACE
#2
ACE
#1
3533