Datasheet

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SLLS102B − DECEMBER 1990 − REVISED MARCH 1996
17
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251−1443
PRINCIPLES OF OPERATION
accessible registers
The system programmer, using the CPU, has access to and control over any of the ACE registers that are
summarized in Table 2. These registers control ACE operations, receive data, and transmit data. Descriptions
of these registers follow Table 3.
Table 3. Summary of Accessible Registers
ADDRESS
REGISTER
REGISTER BIT NUMBER
ADDRESS
REGISTER
MNEMONIC
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
0
RBR
Data
Data
Data
Data
Data
Data
Data
Data
0
RBR
(read only)
Data
Bit 7
(MSB)
Data
Bit 6
Data
Bit 5
Data
Bit 4
Data
Bit 3
Data
Bit 2
Data
Bit 1
Data
Bit 0
(LSB)
(read only)
Bit 7
(MSB)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSB)
0 THR
(write only)
Data
Bit 7
Data
Bit 6
Data
Bit 5
Data
Bit 4
Data
Bit 3
Data
Bit 2
Data
Bit 1
Data
Bit 0
0
THR
(write only)
Data
Bit 7
Data
Bit 6
Data
Bit 5
Data
Bit 4
Data
Bit 3
Data
Bit 2
Data
Bit 1
Data
Bit 0
0
†
DLL Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
1
†
DLM Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
1
IER
0
0
0
0
(EDSSI)
(ERLSI)
(ETBEI)
(ERBFI)
1
IER
0
0
0
0
(EDSSI)
Enable
(ERLSI)
Enable
(ETBEI)
Enable
(ERBFI)
Enable
Enable
modem
Enable
receiver
Enable
transmitter
Enable
received
modem
status
receiver
line
transmitter
holding
received
data
status
interrupt
line
status
holding
register
data
available
interrupt
status
interrupt
register
empty
available
interrupt
interrupt
empty
interrupt
interrupt
2
FCR
Receiver
Receiver
Reserved
Reserved
DMA
Tranmitter
Receiver
FIFO
2
FCR
(write only)
Receiver
Trigger
(MSB)
Receiver
Trigger
(LSB)
Reserved
Reserved
DMA
mode
select
Tranmitter
FIFO
reset
Receiver
FIFO
reset
FIFO
Enable
(write only)
Trigger
(MSB)
Trigger
(LSB)
mode
select
FIFO
reset
FIFO
reset
Enable
2
IIR
FIFOs
‡
FIFOs
‡
0
0
Interrupt ID
‡
Interrupt ID
Interrupt ID
0 If
2
IIR
(read only)
FIFOs
Enabled
‡
FIFOs
Enabled
‡
0
0
Interrupt ID
Bit (2)
‡
Interrupt ID
Bit (1)
Interrupt ID
Bit (0)
0 If
interrupt
pending
(read only)
Enabled
‡
Enabled
‡
Bit (2)
‡
Bit (1)
Bit (0)
interrupt
pending
3
LCR
(DLAB)
Set
Stick
(EPS)
(PEN)
(STB)
(WLSB1)
(WLSB0)
3
LCR
(DLAB)
Divisor latch
access bit
Set
break
Stick
parity
(EPS)
Even parity
select
(PEN)
Parity
enable
(STB)
Number of
stop bits
(WLSB1)
Word length
select bit 1
(WLSB0)
Word length
select bit 0
Divisor latch
access bit
break
parity
Even parity
select
Parity
enable
Number of
stop bits
Word length
select bit 1
Word length
select bit 0
4 MCR 0 0 0 Loop Enable
external
OUT1
(an unused
(RTS)
Request
(DTR)
Data
4
MCR
0
0
0
Loop
Enable
external
interrupt
OUT1
(an unused
internal
(RTS)
Request
to send
(DTR)
Data
terminal
interrupt
(INT0 or
internal
signal)
to send
terminal
ready
(INT0 or
INT1)
signal)
ready
5
LSR
Error in
(TEMT)
(THRE)
(BI)
(FE)
(PE)
(OE)
(DR)
5
LSR
Error in
receiver
FIFO
‡
(TEMT)
Transmitter
empty
(THRE)
Transmitter
holding
(BI)
Break
interrupt
(FE)
Framing
error
(PE)
Parity
error
(OE)
Overrun
error
(DR)
Data
ready
receiver
FIFO
‡
Transmitter
empty
Transmitter
holding
register
Break
interrupt
Framing
error
Parity
error
Overrun
error
Data
ready
FIFO
empty
holding
register
empty
interrupt
error
error
error
ready
register
empty
6
MSR
(DCD)
(RI)
(DSR)
(CTS)
(
∆
DCD)
(TERI)
(
∆
DSR)
(
∆
CTS)
6
MSR
(DCD)
Data carrier
detect
(RI)
Ring
indicator
(DSR)
Data set
ready
(CTS)
Clear
to send
(∆DCD)
Delta
data carrier
(TERI)
Trailing
edge ring
(∆DSR)
Delta
data set
(∆CTS)
Delta
clear
Data carrier
detect
Ring
indicator
Data set
ready
Clear
to send
Delta
data carrier
detect
Trailing
edge ring
indicator
Delta
data set
ready
Delta
clear
to send
detect
indicator
ready
to send
data carrier
detect
edge ring
indicator
data set
ready
clear
to send
7 SCR Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
†
DLAB = 1
‡
These bits are always 0 when FIFOs are disabled.