Datasheet

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SLLS102B − DECEMBER 1990 − REVISED MARCH 1996
13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251−1443
PARAMETER MEASUREMENT INFORMATION
ActiveActive
Top Byte of FIFO
IOR
(RD LSR)
CLK
Sample
SIN
Active
Time Out or
Trigger Level
Interrupt
LSI
Interrupt
IOR
(RD RBR)
(FIFO at or above
trigger level)
(FIFO below
trigger level)
Previous Byte
Read From FIFO
Stop
t
d9
(see Note A)
t
pd6
t
d9
t
pd6
50% 50%
50%50%
50%
50% 50%
Figure 11. Receiver FIFO After First Byte (After RDR Set) Waveforms
Active
IOR
(RD RBR)
CLK
Sample
SIN
(first byte)
Stop
t
d9
(see Note B )
RXRDY
t
pd7
See Note A
50%
50%50%
Figure 12. Receiver Ready Mode 0 Waveforms
NOTES: A. This is the reading of the last byte in the FIFO.
B. When FCR0=1, then t
d9
= 3 RCLK cycles. For a time-out interrupt, t
d9
= 8 RCLK cycles.