Datasheet


   
 
SLLS102B − DECEMBER 1990 − REVISED MARCH 1996
12
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251−1443
PARAMETER MEASUREMENT INFORMATION
t
pd6
ParityData Bits 58
Stop
Start
t
pd5
8
CLK
Cycles
t
d9
RCLK
CLK
TL16C450 MODE
SIN
(receiver
input
data)
Sample
CLK
Interrupt
(data
ready
or
RCVR
ERR)
IOR
Active
50%
50%
50%
Figure 9. Receiver Timing Waveforms
Trigger
Interrupt
(FCR6,
7=0,
0)
Active
ParityData Bits 58
Stop
Start
t
pd6
Active
t
pd6
t
d9
SIN
Sample
CLK
IOR
(RD LSR)
Line Status
Interrupt (LSI)
IOR
(RD RBR)
(FIFO at or above
trigger level)
(FIFO below
trigger level)
50%
50%
50%
50%
50%
50%
Figure 10. Receiver FIFO First Byte (Sets RDR) Waveforms