SLLS102B − DECEMBER 1990 − REVISED MARCH 1996 D IBM PC/AT Compatible D Programmable Serial Interface Characteristics for Each Channel: − 5-, 6-, 7-, or 8-bit Characters − Even-, Odd-, or No-Parity Bit Generation and Detection − 1-, 1 1/2-, or 2-Stop Bit Generation D Two TL16C550 ACEs D Enhanced Bidirectional Printer Port D 16-Byte FIFOs Reduce CPU Interrupts D Independent Control of Transmit, Receive, D 3-State TTL Drive for the Data and Contr
SLLS102B − DECEMBER 1990 − REVISED MARCH 1996 description (continued) received from peripheral devices or modems and parallel-to-serial conversion on data characters transmitted by the CPU. The complete status of each channel of the dual ACE can be read at any time during functional operation by the CPU. The information obtained includes the type and condition of the transfer operations being performed and the error conditions.
SLLS102B − DECEMBER 1990 − REVISED MARCH 1996 Terminal Functions TERMINAL NAME NO. I/O DESCRIPTION ACK 68 I Line printer acknowledge. ACK goes low to indicate a successful data transfer has taken place. It generates a printer port interrupt during its positive transition. AFD 56 I/O Line printer autofeed.
SLLS102B − DECEMBER 1990 − REVISED MARCH 1996 Terminal Functions (continued) TERMINAL I/O DESCRIPTION 45, 60 O Serial channel interrupts.
SLLS102B − DECEMBER 1990 − REVISED MARCH 1996 Terminal Functions (continued) TERMINAL NAME NO. I/O DESCRIPTION STB 55 I/O Printer strobe. STB is an open-drain line that provides communication between the TL16C552 and the printer. When it is active (low), it provides the printer with a signal to latch the data currently on the parallel port. This terminal has an internal pullup resistor to VDD of approximately 10 kΩ.
SLLS102B − DECEMBER 1990 − REVISED MARCH 1996 electrical characteristics over recommended ranges of operating free-air temperature and supply voltage PARAMETER TEST CONDITIONS High-level output voltage IOH = − 0.4 mA for DB0 −DB7, IOH = − 2 mA for PD0 −PD7, IOH = − 0.4 mA for INIT, AFD, STB, and SLIN (see Note 2), IOH = − 0.
SLLS102B − DECEMBER 1990 − REVISED MARCH 1996 write cycle timing requirements over recommended ranges of operating free-air temperature and supply voltage (see Figure 5) MIN MAX UNIT tw5 tsu4 Pulse duration, IOW low 80 ns Setup time, chip select valid before IOW low (see Note 3) 15 ns tsu5 tsu6 Setup time, A2 −A0 valid before IOW low (see Note 3) 15 ns Setup time, D0 −D7 valid before IOW high 15 ns th3 th4 Hold time, A2 −A0 valid a
SLLS102B − DECEMBER 1990 − REVISED MARCH 1996 receiver switching characteristics over recommended ranges of operating free-air temperature and supply voltage (see Figures 9, 10, 11, 12 and 13) PARAMETER TEST CONDITIONS td9 Delay time from stop to INT high tpd5 tpd6 Propagation delay time from RCLK high to sample CLK high MIN See Note 7 MAX UNIT 1 RCLK cycle 100 ns Propagation delay time from IOR (RD RBR/RD LSR) high to reset interrupt lo
SLLS102B − DECEMBER 1990 − REVISED MARCH 1996 PARAMETER MEASUREMENT INFORMATION tw1 2V CLK (XTAL1) 0.8 V tw2 fclock = 8 MHz MAX Figure 1. Clock Input (CLK) Voltage Waveform 2.54 V Device Under Test 680 Ω TL16C552 82 pF† †Includes scope and jig capacitance Figure 2.
SLLS102B − DECEMBER 1990 − REVISED MARCH 1996 PARAMETER MEASUREMENT INFORMATION Valid 50 % A2, A1, A0 50 % th1 CS0, CS1, CS2 50 % Valid 50 % th2 td1 tsu1 tsu2 IOR Active 50 % 50 % 50 % td2 tw4 OR IOW 50 % Active tpd1 tpd1 BDO Active 50 % 50 % tdis ten Data D0 −D7 Valid Data Figure 4.
SLLS102B − DECEMBER 1990 − REVISED MARCH 1996 PARAMETER MEASUREMENT INFORMATION Start Serial Out (SOUT) Data Bits 5 −8 50 % Stop (1− 2) Parity td5 Interrupt (THRE) 50 % 50 % td6 50 % tpd2 50 % 50 % tpd2 td7 IOW (WR THR) 50 % Start 50 % 50 % 50 % tpd3 IOR (RD IIR) 50 % Figure 6. Transmitter Timing Waveforms IOW (WR THR) SOUT Byte #1 50 % Data Parity 50 % Start Stop td8 tpd4 TXRDY 50 % 50 % Figure 7.
SLLS102B − DECEMBER 1990 − REVISED MARCH 1996 PARAMETER MEASUREMENT INFORMATION RCLK tpd5 8 CLK Cycles CLK TL16C450 MODE SIN (receiver input data) Start Data Bits 5 −8 Parity Stop Sample CLK td9 Interrupt (data ready or RCVR ERR) 50 % 50 % tpd6 Active IOR 50 % Figure 9.
SLLS102B − DECEMBER 1990 − REVISED MARCH 1996 PARAMETER MEASUREMENT INFORMATION SIN Stop Sample CLK td9 (see Note A) Time Out or Trigger Level Interrupt 50 % (FIFO at or above trigger level) 50 % (FIFO below trigger level) tpd6 LSI Interrupt 50 % Top Byte of FIFO tpd6 td9 IOR (RD LSR) 50 % Active IOR (RD RBR) 50 % 50 % Active 50 % Active Previous Byte Read From FIFO Figure 11.
SLLS102B − DECEMBER 1990 − REVISED MARCH 1996 PARAMETER MEASUREMENT INFORMATION IOR (RD RBR) Active 50 % See Note A SIN (first byte that reaches the trigger level) Stop Sample CLK td9 (see Note B) RXRDY 50 % 50 % tpd7 NOTES: A. This is the reading of the last byte in the FIFO. B. When FCR0=1, then td9 = 3 RCLK cycles. For a trigger change level interrupt, td9 = 8 RCLK Figure 13.
SLLS102B − DECEMBER 1990 − REVISED MARCH 1996 PARAMETER MEASUREMENT INFORMATION DATA Valid 50 % 50 % tsu7 STB th6 50 % 50 % tw6 ACK 50 % ÉÉÉÉ ÉÉÉÉ ÉÉÉÉ 50 % tw6 td10 BUSY 50 % td12 td11 50 % 50 % tw7 Figure 15. Parallel Port Timing Waveforms RESET 50 % 50 % tw3 Figure 16.
SLLS102B − DECEMBER 1990 − REVISED MARCH 1996 PRINCIPLES OF OPERATION Three types of information are stored in the internal registers used in the ACE: control, status, and data. Mnemonic abbreviations are shown in the Table 1 for the registers. Table 1.
SLLS102B − DECEMBER 1990 − REVISED MARCH 1996 PRINCIPLES OF OPERATION accessible registers The system programmer, using the CPU, has access to and control over any of the ACE registers that are summarized in Table 2. These registers control ACE operations, receive data, and transmit data. Descriptions of these registers follow Table 3. Table 3.
SLLS102B − DECEMBER 1990 − REVISED MARCH 1996 PRINCIPLES OF OPERATION FIFO control register (FCR) This write-only register is at the same location as the IIR. It enables and clears the FIFOs, sets the trigger level of the receiver FIFO, and selects the type of DMA signaling. The contents of FCR are described in Table 3 and the following bulleted list. D Bit 0: FCR0 enables both the transmitter and receiver FIFOs.
SLLS102B − DECEMBER 1990 − REVISED MARCH 1996 PRINCIPLES OF OPERATION FIFO interrupt mode operation (continued) 1. A FIFO timeout interrupt occurs when the following conditions exist: a. Minimum of one character in FIFO b. Last received serial character was longer than four continuous previous character times ago (if two stop bits are programmed, the second one is included in the time delay). c.
SLLS102B − DECEMBER 1990 − REVISED MARCH 1996 PRINCIPLES OF OPERATION interrupt enable register (IER) (continued) D D D D Bit 1: IER1, when set, enables the THRE interrupt. Bit 2: IER2, when set, enables the receiver line status interrupt. Bit 3: IER3, when set, enables the modem status interrupt. Bits 4 − 7: IER4 − IER7 are always cleared.
SLLS102B − DECEMBER 1990 − REVISED MARCH 1996 PRINCIPLES OF OPERATION line control register (LCR) The format of the data character is controlled by the LCR. The LCR may be read. Its contents are described in the following bulleted list and shown in Figure 17. D Bits 0 and 1: LCR0 and LCR1 are the word length select bits. The number of bits in each serial character is programmed as shown in Figure 17. D Bit 2: LCR2 is the stop bit select bit.
SLLS102B − DECEMBER 1990 − REVISED MARCH 1996 PRINCIPLES OF OPERATION line control register (LCR) (continued) LINE CONTROL REGISTER LCR LCR LCR LCR LCR LCR LCR LCR 7 6 5 4 3 2 1 0 Word Length Select 0 0 1 1 0 = 5 Data Bits 1 = 6 Data Bits 0 = 7 Data Bits 1 = 8 Data Bits Stop Bit Select 0 = 1 Stop Bits 1 = 1.
SLLS102B − DECEMBER 1990 − REVISED MARCH 1996 PRINCIPLES OF OPERATION line printer port (LPT) (continued) Table 6 summarizes the possible combinations of extended mode and the direction control bit. In either case, the bits of the LPD register are defined as follows: Table 6.
SLLS102B − DECEMBER 1990 − REVISED MARCH 1996 PRINCIPLES OF OPERATION line printer port (LPT) (continued) Table 8. LPC Register Bit Description BIT DESCRIPTION 0 STB 1 AFD 2 INIT 3 SLIN 4 INT2 EN 5 DIR 6 Reserved (0) 7 Reserved (0) D Bit 0: This bit is the printer strobe (STB) control bit. When this bit is set, the STB signal is asserted on the LPT interface. When STB is cleared, the signal is negated.
SLLS102B − DECEMBER 1990 − REVISED MARCH 1996 PRINCIPLES OF OPERATION line status register (LSR) (continued) D Bit 0: LSR0 is the data ready (DR) bit. DR is set high when an incoming character has been received and transferred into the receiver buffer register or the FIFO. LSR0 is cleared by a CPU read of the data in the receiver buffer register or the FIFO. D Bit 1: SR1 is the overrun error (OE) bit.
SLLS102B − DECEMBER 1990 − REVISED MARCH 1996 PRINCIPLES OF OPERATION master reset After power up, the ACE RESET input should be held low for one microsecond to reset the ACE circuits to an idle mode until initialization. A low on RESET causes the following: 1. It initializes the transmitter and receiver clock counters. 2. It clears the LSR, except for TEMT and THRE, which are set. The MCR is also cleared.
SLLS102B − DECEMBER 1990 − REVISED MARCH 1996 PRINCIPLES OF OPERATION modem control register (MCR) The MCR controls the interface with the modem or data set as described in Figure 18. The MCR can be written to and read from. The RTS and DTR outputs are directly controlled by their control bits in this register. A high input asserts a low (true) at the output terminals.
SLLS102B − DECEMBER 1990 − REVISED MARCH 1996 PRINCIPLES OF OPERATION modem status register (MSR) The MSR provides the CPU with status of the modem input lines from the modem or peripheral devices.
SLLS102B − DECEMBER 1990 − REVISED MARCH 1996 PRINCIPLES OF OPERATION modem status register (MSR) (continued) Reading the MSR register clears the delta modem status indications but has no affect on the other status bits. For LSR and MSR, the setting of status bits is inhibited during status register read operations. When a status condition is generated during a read IOR operation, the status bit is not set until the trailing edge of the read.
SLLS102B − DECEMBER 1990 − REVISED MARCH 1996 PRINCIPLES OF OPERATION programmable baud generator The ACE serial channel contains a programmable baud rate generator that divides the clock (dc to 8 MHz) by any divisor from 1 to (216 −1). The output frequency of the baud rate generator is 16 × the data rate (divisor # = clock ÷ (baud rate × 16)) referred to in this document as RCLK.
SLLS102B − DECEMBER 1990 − REVISED MARCH 1996 PRINCIPLES OF OPERATION programmable baud generator (continued) Table 16. Baud Rates Using a 8.192-MHz Crystal BAUD RATE DESIRED 50 75 110 134.
SLLS102B − DECEMBER 1990 − REVISED MARCH 1996 PRINCIPLES OF OPERATION scratchpad register The scratch register is an 8-bit read/write register that has no affect on either channel in the ACE. It is intended to be used by the programmer to temporarily hold data.
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