Datasheet

TL16C552A, TL16C552AM
DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH FIFO
SLLS189D – NOVEMBER 1994 – REVISED JANUARY 1999
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
recommended operating conditions
MIN NOM MAX UNIT
Supply voltage, V
DD
4.75 5 5.25 V
Clock high-level input voltage, V
IH(CLK)
2 V
DD
V
Clock low-level input voltage, V
IL(CLK)
0 0.8 V
High-level input voltage, V
IH
2 V
DD
V
Low-level input voltage, V
IL
0 0.8 V
Clock frequency, f
clock
16 MHz
O
p
erating free air tem
p
erature T
A
I suffix –40 85
°
C
Operating
free
-
air
temperat
u
re
,
T
A
M suffix –55 125
°C
package thermal characteristics
PARAMETER
TEST CONDITIONS
FN Package HV Package
UNIT
PARAMETER
TEST
CONDITIONS
MIN TYP MAX MIN TYP MAX
UNIT
R
θJA
Junction-to-ambient thermal impedance Board mounted, no air flow 52 74 °C/W
R
θJC
Junction-to-case thermal impedance 14 3 °C/W
T
J
Junction temperature 115 150 °C/W
electrical characteristics over recommended ranges of operating free-air temperature and supply
voltage (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN MAX UNIT
V
OH
High-level output voltage
I
OH
= –12 mA for PD0 –PD7,
I
OH
= –4 mA for all other outputs (see Note 2),
2.4 V
V
OL
Low-level output voltage
I
OL
= 12 mA for PD0– PD7,
I
OL
= 12 mA for INIT
, AFD, STB, and SLIN,
I
OL
= 4 mA for all other outputs
0.4 V
I
I
Input current
V
DD
= 5.25 V (see Note 3),
All other terminals are floating
±10 µA
I
I(CLK)
Clock input current V
I
= 0 to 5.25 V ±10 µA
V
DD
=525V V
O
= 0 with chi
p
deselected or
I
OZ
Hi
g
h-impedance output current
V
DD
=
5
.
25
V
,
V
O
=
0
with
chi
deselected
or
V
O
5 25 V with chip and write mode selected (see Note 2)
±20
µ
A
I
OZ
High im edance
out ut
current
V
O
=
5
.
25
V
w
ith
c
hi
p an
d
wr
it
e mo
d
e se
l
ec
t
e
d
(
see
N
o
t
e
2)
±20
µA
V 5 25 V No loads on outputs
I
DD
Su
pp
ly current
V
DD
=
5
.
25
V
,
N
o
l
oa
d
s on ou
t
pu
t
s,
50
mA
I
DD
S
u
ppl
y
c
u
rrent
DD
In
p
utsat08Vor2V f
clock
= 8 MHz
50
mA
In uts
at
0
.
8
V
or
2
V
,
f
clock
=
8
MHz
NOTES: 2. Excluding INIT, AFD, STB, and SLIN. They are open-drain terminals with an internal pullup resistor to V
DD
of approximately 10 KΩ.
3. Excluding the TRI input terminal. It contains an internal pulldown resistor of approximately 5 kΩ.
clock timing requirements over recommended ranges of operating free-air temperature and supply
voltage
MIN MAX UNIT
t
w1
Pulse duration, CLK ↑ (external clock) (see Figure 1) 31 ns
t
w2
Pulse duration, CLK ↓ (external clock) (see Figure 1) 31 ns
t
w3
Pulse duration, RESET 1000 ns