Datasheet

TL16C552A, TL16C552AM
DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH FIFO
SLLS189D – NOVEMBER 1994 – REVISED JANUARY 1999
19
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
accessible registers
Using the CPU, the system programmer has access to and control over any of the ACE registers that are
summarized in Table 1. These registers control ACE operations, receive data, and transmit data. Descriptions
of these registers follow Table 3.
Table 3. Summary of Accessible Registers
ADDRESS
REGISTER
REGISTER BIT NUMBER
ADDRESS
MNEMONIC
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
0 RBR
(read only)
Data Bit 7
(MSB)
Data Bit 6 Data Bit 5 Data Bit 4 Data Bit 3 Data Bit 2 Data Bit 1 Data Bit 0
(LSB)
0 THR Data Data Data Data Data Data Data Data
(write only) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
0
†
DLL Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
1
†
DLM Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
1 IER 0 0 0 0
(
EDSSI
)
Enable
(
ERLSI
)
(
ETBEI
)
(
ERBFI
)
1
IER
0
0
0
0
(EDSSI)
Enable
modem status
(ERLSI)
Enable
(ETBEI)
Enable
(ERBFI)
Enable
modem
status
interrupt
Enable
receiver line
Enable
transmitter
Enable
received
status holding data
interrupt
g
register available
g
empty interrupt
interrupt
2
FCR
Receiver
Receiver
Reserved
Reserved
DMA
Transmitter
Receiver
FIFO
2
FCR
(write only)
Receiver
trigger (MSB)
Receiver
trigger (LSB)
Reserved
Reserved
DMA
mode select
Transmitter
FIFO reset
Receiver
FIFO reset
FIFO
enable
(
wr
it
e on
l
y
)
t
r
i
gger
(MSB)
t
r
i
gger
(LSB)
mo
d
e se
l
ec
t
FIFO
rese
t
FIFO
rese
t
ena
bl
e
2 IIR FIFOs
‡
FIFOs
‡
0 0 Interrupt ID
‡
Interrupt ID Interrupt ID 0 if
(read only) enabled
‡
enabled
‡
bit 3
‡
bit 2 bit 1 interrupt
pending
3 LCR (DLAB) Set Stick (EPS) (PEN) (STB) (WLSB1) (WLSB0)
()
Divisor latch break parity
()
Even parity
()
Parity enable
()
Number of
()
Word length
()
Word length
access bit select stop bits select bit 1 select bit 0
4 MCR 0 0 0 Loop OUT2 Enable OUT1 (RTS) (DTR)
external (an unused
()
Request
()
Data
interrupt
(INT0 INT1)
internal
il)
to send terminal
d
(INT
0 or
INT
1
)
s
i
gna
l)
rea
d
y
5 LSR Error in (TEMT) (THRE) (BI) (FE) (PE) (OE) (DR)
receiver
‡
()
Transmitter
()
Transmitter
()
Break
()
Framing
()
Parity
()
Overrun
()
Data
FIFO
‡
empty holding
it
interrupt error error error ready
reg
i
ster
em
p
ty
empty
6
MSR
(DCD)
(RI)
(DSR)
(CTS)
(∆DCD)
(TERI)
(∆DSR)
(∆CTS)
6
MSR
(DCD)
Data carrier
(RI)
Ring
(DSR)
Data set
(CTS)
Clear
(∆DCD)
Delta data
(TERI)
Trailing edge
(∆DSR)
Delta data
(∆CTS)
Delta clear
Data
carrier
detect
Ring
indicator
Data
set
ready
Clear
to send
Delta
data
carrier detect
Trailing
edge
ring indicator
Delta
data
set ready
Delta
clear
clear to send
detect
indicator
ready
to
send
carrier
detect
ring
indicator
set
ready
clear
to
send
7 SCR Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
†
DLAB = 1
‡
These bits are always 0 when FIFOs are disabled.