Datasheet

TL16C552A, TL16C552AM
DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH FIFO
SLLS189D – NOVEMBER 1994 – REVISED JANUARY 1999
13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
IOW
(WR THR)
t
d8
t
pd5
SOUT
TXRDY
Byte #16
ParityData Stop
Start
Start of
Byte #16
FIFO Full
50%
50% 50%
Figure 8. Transmitter Ready Mode 1 Timing Waveforms
ParityData Bits 5–8
Stop
Start
t
pd6
t
d9
RCLK
CLK
TL16C450 Mode
SIN
(receiver input
data)
Sample
CLK
Interrupt
(data ready or
RCVR ERR)
IOR
Active
t
pd7
50%
50%
50%
8 CLK Cycles
Figure 9. Receiver Timing Waveforms