Datasheet

TL16C552A, TL16C552AM
DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH FIFO
SLLS189D – NOVEMBER 1994 – REVISED JANUARY 1999
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
parallel port timing requirements over recommended ranges of supply voltage and operating
free-air temperature (see Note 16 and Figures 15, 16, and 17)
MIN MAX UNIT
t
su7
Setup time, data valid before STB ↓ 1 µs
t
h6
Hold time, data valid after STB ↑ 1 µs
t
w6
Pulse duration, STB ↓ 1 µs
t
d10
Delay time, BUSY ↑ to ACK ↓ Defined by printer
t
d11
Delay time, BUSY ↓ to ACK ↓ Defined by printer
t
w7
Pulse duration, BUSY ↑ Defined by printer
t
w8
Pulse duration, ACK ↓ Defined by printer
t
d12
Delay time, BUSY ↑ after STB ↑ Defined by printer
t
d13
Delay time, INT2 ↓ after ACK ↓ (see Note 17) 22 ns
t
d14
Delay time, INT2 ↑ after ACK ↑ (see Note 17) 20 ns
t
d15
Delay time, INT2 ↑ after ACK ↑ (see Note 17) 24 ns
t
d16
Delay time, INT2 ↓ after IOR ↑ (see Note 17) 25 ns
NOTES: 16. These parameters are not production tested.
17. t
d13
–t
d16
are all measured with a 15-pF load.
PARAMETER MEASUREMENT INFORMATION
2 V
0.8 V
CLK (XTAL1)
t
w1
t
w2
f
clock
= 16 MHz MAX
2 V
0.8 V
Figure 1. CLK Voltage Waveform
Device Under Test
680 Ω
82 pF
(see Note A)
2.54 V
TL16C552A
NOTE A: This includes scope and jig capacitance.
Figure 2. Output Load Circuit