Datasheet

Modem Status Register (MSR)
TL16C550D , , TL16C550DI
SLLS597E – APRIL 2004 – REVISED DECEMBER 2008 .................................................................................................................................................. www.ti.com
• Bit 3: This bit (OUT2) controls OUT2, a user-designated output signal.
When any of bits 0 through 3 are set, the associated output is forced low. When any of these bits are cleared,
the associated output is forced high.
• Bit 4: This bit (LOOP) provides a local loop back feature for diagnostic testing of the ACE. When LOOP is set,
the following occurs:
– The transmitter SOUT is set high.
– The receiver SIN is disconnected.
– The output of the TSR is looped back into the receiver shift register input.
– The four modem control inputs ( CTS, DSR, DCD, and RI) are disconnected.
– The four modem control outputs ( DTR, RTS, OUT1, and OUT2) are internally connected to the four
modem control inputs.
– The four modem control outputs are forced to the inactive (high) levels.
• Bit 5: This bit (AFE) is the autoflow control enable. When set, the autoflow control as described in the detailed
description is enabled.
In the diagnostic mode, data that is transmitted is immediately received. This allows the processor to verify
the transmit and receive data paths to the ACE. The receiver and transmitter interrupts are fully operational.
The modem control interrupts are also operational, but the modem control interrupt's sources are now the
lower four bits of the MCR instead of the four modem control inputs. All interrupts are still controlled by the
IER.
The ACE flow can be configured by programming bits 1 and 5 of the MCR as shown in Table 8 .
Table 8. ACE Flow Configuration
MCR BIT 5 MCR BIT 1
ACE FLOW CONFIGURATION
(AFE) (RTS)
1 1 Auto- RTS and auto- CTS enabled (autoflow control enabled)
1 0 Auto- CTS only enabled
0 X Auto- RTS and auto- CTS disabled
The MSR is an 8-bit register that provides information about the current state of the control lines from the
modem, data set, or peripheral device to the CPU. Additionally, four bits of this register provide change
information; when a control input from the modem changes state, the appropriate bit is set. All four bits are
cleared when the CPU reads the MSR. The contents of this register are summarized in Table 3 and are
described in the following bulleted list.
• Bit 0: This bit is the change in clear-to-send ( Δ CTS) indicator. Δ CTS indicates that the CTS input has
changed state since the last time it was read by the CPU. When Δ CTS is set (autoflow control is not enabled
and the modem status interrupt is enabled), a modem status interrupt is generated. When autoflow control is
enabled ( Δ CTS is cleared), no interrupt is generated.
• Bit 1: This bit is the change in data set ready ( Δ DSR) indicator. Δ DSR indicates that the DSR input has
changed state since the last time it was read by the CPU. When Δ DSR is set and the modem status interrupt
is enabled, a modem status interrupt is generated.
• Bit 2: This bit is the trailing edge of the ring indicator (TERI) detector. TERI indicates that the RI input to the
chip has changed from a low to a high level. When TERI is set and the modem status interrupt is enabled, a
modem status interrupt is generated.
• Bit 3: This bit is the change in data carrier detect ( Δ DCD) indicator. Δ DCD indicates that the DCD input to the
chip has changed state since the last time it was read by the CPU. When Δ DCD is set and the modem status
interrupt is enabled, a modem status interrupt is generated.
• Bit 4: This bit is the complement of the clear-to-send ( CTS) input. When the ACE is in the diagnostic test
mode (LOOP [MCR4] = 1), this bit is equal to the MCR bit 1 (RTS).
• Bit 5: This bit is the complement of the data set ready ( DSR) input. When the ACE is in the diagnostic test
mode (LOOP [MCR4] = 1), this bit is equal to the MCR bit 0 (DTR).
• Bit 6: This bit is the complement of the ring indicator ( RI) input. When the ACE is in the diagnostic test mode
(LOOP [MCR4] = 1), this bit is equal to the MCR bit 2 (OUT1).
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