Datasheet

PRINCIPLES OF OPERATION
Accessible Registers
TL16C550D , , TL16C550DI
SLLS597E – APRIL 2004 – REVISED DECEMBER 2008 .................................................................................................................................................. www.ti.com
Table 1. Register Selection
DLAB
(1)
A2 A1 A0 REGISTER
0 L L L Receiver buffer (read), transmitter holding register (write)
0 L L H Interrupt enable register
X L H L Interrupt identification register (read only)
X L H L FIFO control register (write)
X L H H Line control register
X H L L Modem control register
X H L H Line status register
X H H L Modem status register
X H H H Scratch register
1 L L L Divisor latch (LSB)
1 L L H Divisor latch (MSB)
(1) The divisor latch access bit (DLAB) is the most significant bit (MSB) of the line control register. The
DLAB signal is controlled by writing to this bit location (see Table 4 ).
Table 2. ACE Reset Functions
REGISTER/SIGNAL RESET CONTROL RESET STATE
Interrupt enable register Master reset All bits cleared (0 − 3 forced and 4 − 7 permanent)
Bit 0 is set, bits 1, 2, 3, 6, and 7 are cleared, and bits
Interrupt identification register Master reset
4 − 5 are permanently cleared
FIFO control register Master reset All bits cleared
Line control register Master reset All bits cleared
Modem control register Master reset All bits cleared (6 − 7 permanent)
Line status register Master reset Bits 5 and 6 are set; all other bits are cleared
Modem status register Master reset Bits 0 − 3 are cleared; bits 4 − 7 are input signals
SOUT Master reset High
INTRPT (receiver error flag) Read LSR/MR Low
INTRPT (received data available) Read RBR/MR Low
INTRPT (transmitter holding register empty) Read IR/write THR/MR Low
INTRPT (modem status changes) Read MSR/MR Low
OUT2 Master reset High
RTS Master reset High
DTR Master reset High
OUT1 Master reset High
Scratch register Master reset No effect
Divisor latch (LSB and MSB) registers Master reset No effect
Receiver buffer register Master reset No effect
Transmitter holding register Master reset No effect
RCVR FIFO MR/FCR1 – FCR0/ Δ FCR0 All bits cleared
XMIT FIFO MR/FCR2 – FCR0/ Δ FCR0 All bits cleared
The system programmer, using the CPU, has access to and control over any of the ACE registers that are
summarized in Table 2 . These registers control ACE operations, receive data, and transmit data. Descriptions of
these registers follow Table 3 .
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